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    System and method for random data distribution in a memory array
    1.
    发明授权
    System and method for random data distribution in a memory array 有权

    公开(公告)号：US12079478B2

    公开(公告)日：2024-09-03

    申请号：US18067744

    申请日：2022-12-19

    申请人： GSI Technology Inc.

    发明人： Avidan Akerib

    IPC分类号： G06F3/06

    CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0679

    摘要： A method for random data distribution in a memory array from a source row to a destination row includes receiving a plurality of pairs of addresses, where each pair includes a source address of a source cell in the source row and a destination addresses of a destination cell in a destination row, storing the source address in cells of a column associated with the destination cell, creating a Boolean algebra expression defining a correlation between each one of the source addresses and a value stored in each one of the source cells, where applying the Boolean algebra expression on any one of the source addresses provides a value of one of the source cells, concurrently applying the Boolean algebra expression on a plurality of columns storing the source addresses and concurrently writing a plurality of results on the destination row.

    PIPELINE ARCHITECTURE FOR BITWISE MULTIPLIER-ACCUMULATOR (MAC)
    2.
    发明公开
    PIPELINE ARCHITECTURE FOR BITWISE MULTIPLIER-ACCUMULATOR (MAC) 审中-公开

    公开(公告)号：US20240192962A1

    公开(公告)日：2024-06-13

    申请号：US18444695

    申请日：2024-02-18

    申请人： GSI Technology Inc.

    发明人： Avidan AKERIB

    IPC分类号： G06F9/38 ,  G06F7/544 ,  G06F9/30

    CPC分类号： G06F9/3893 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30079

    摘要： A unit for accumulating a plurality of multiplied bit values includes a first row and a second row of input units, a bit-wise multiplier and a bit-wise accumulator. The first row receives a pipeline of the bits of a multiplicand A and the second row, to the left of the first row, receives a pipeline of the bits of a multiplicand B. The bit-wise multiplier, below the first row of input units, includes multiplier bit-line processors formed into rows and columns. Some rows of the bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with one bit of a current multiplicand B and some rows of the bit-wise multiplier handle sum and carry values between the bits. The bit-wise accumulator, to the right of the bit-wise multiplier, includes a column of accumulator bit-line processors. Each accumulator bit-line processor accumulates output of a row of the bit-wise multiplier.

    Associative hash tree
    3.
    发明授权
    Associative hash tree 有权

    公开(公告)号：US11991290B2

    公开(公告)日：2024-05-21

    申请号：US17665610

    申请日：2022-02-07

    申请人： GSI Technology Inc.

    发明人： Dan Ilan

    IPC分类号： H04L9/32 ,  H04L9/06

    CPC分类号： H04L9/3239 ,  H04L9/0643

    摘要： A system to dynamically calculate a root hash value from a plurality of leaf hash values includes a flat associative memory and a hash parser. The flat associative memory stores a plurality of leaf hash values. The hash parser extracts a compressed number of branch nodes from the plurality of leaf hash values, determines branch node relationships from the plurality of leaf hash values, and saves the compressed number of branch nodes, and the branch node relationships.

    CONCURRENT MULTI-BIT SUBTRACTION IN ASSOCIATIVE MEMORY
    5.
    发明公开
    CONCURRENT MULTI-BIT SUBTRACTION IN ASSOCIATIVE MEMORY 审中-公开

    公开(公告)号：US20230266911A1

    公开(公告)日：2023-08-24

    申请号：US17678073

    申请日：2022-02-23

    申请人： GSI Technology Inc.

    发明人： Moshe LAZER ,  Eyal AMIEL

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

    摘要： A method for an associative memory device includes storing a plurality of pairs of multi-bit operands X and Y in rows of a memory array of the associative memory device, each pair in a different column of the memory array. Cells in a column are connected by a first bit-line providing a value of activated cells and a second bit-line providing an inverse value of the activated cells. The bits of X are stored in first rows and the bits of Y are stored in second rows. The method includes reading an inverse value of a bit stored in each of the second rows using the second bit-line, writing it to third rows and concurrently, on all columns, performing multi-bit add operations between a value of X, an inverse value of Y and a carry-in bit initiated to 1, providing the difference between X and Y in each of the columns.

    Memory device for determining an extreme value
    6.
    发明授权
    Memory device for determining an extreme value 有权

    公开(公告)号：US11670369B2

    公开(公告)日：2023-06-06

    申请号：US17384873

    申请日：2021-07-26

    申请人： GSI Technology Inc.

    发明人： Avidan Akerib ,  Eli Ehrman

    IPC分类号： G11C15/00 ,  G11C15/04

    CPC分类号： G11C15/00 ,  G11C15/046

    摘要： A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.

    CORDIC COMPUTATION OF SIN/COS USING COMBINED APPROACH IN ASSOCIATIVE MEMORY
    7.
    发明申请
    CORDIC COMPUTATION OF SIN/COS USING COMBINED APPROACH IN ASSOCIATIVE MEMORY 有权

    公开(公告)号：US20220413799A1

    公开(公告)日：2022-12-29

    申请号：US17741481

    申请日：2022-05-11

    申请人： GSI Technology Inc.

    发明人： Moshe LAZER ,  Samuel LIFSCHES ,  Almog LEVY

    IPC分类号： G06F7/48

    摘要： A method for an associative memory device includes the steps of providing a look up table (LUT) with all possible solutions for N first iterations of a CORDIC algorithm, receiving a plurality of input angles, concurrently computing a location index for each angle of the plurality of angles and concurrently storing each index in a column of the associative memory device, copying a solution from the LUT in the location index to a plurality of columns associated with the index and concurrently performing M additional iterations of the CORDIC algorithm on the columns to compute a value of a trigonometric function for each angle.

    SYSTEM AND METHOD FOR PARALLEL COMBINATORIAL DESIGN
    9.
    发明申请
    SYSTEM AND METHOD FOR PARALLEL COMBINATORIAL DESIGN 有权

    公开(公告)号：US20220244959A1

    公开(公告)日：2022-08-04

    申请号：US17590837

    申请日：2022-02-02

    申请人： GSI Technology Inc.

    发明人： Dan ILAN

    IPC分类号： G06F9/30 ,  G06F17/16

    摘要： A system for parallel combinatorial design includes a processor, an in-memory vector processor and a storage unit. The processor includes a seed generator, a Cspan generator and a rule checker. The seed generator generates at least one seed to generate combinations of length N, defining a space of N choices of which M choices are to be selected. The Cspan generator generates at least one combination from the at least one seed and stores each combination in a separate column of the in-memory vector processor. The rule checker performs a parallel search at least in the in-memory vector processor for combinations which satisfy a rule and the storage unit receives search results of the rule checker from the in-memory vector processor.