MOLD UNIT FOR MANUFACTURING MICROSTRUCTURES

    公开(公告)号:US20250001651A1

    公开(公告)日:2025-01-02

    申请号:US18708703

    申请日:2022-11-09

    Abstract: Disclosed is a mold unit for manufacturing microstructures, the mold unit comprising a first mold for manufacturing microstructures in which a plurality of microneedles are formed on one surface of a base layer. The first mold comprises: a first base part in which first needle grooves for forming the microneedles are formed on the upper surface, and which includes a first embankment protruding to a predetermined height around the region where the first needle grooves are formed; a first edge part which is provided along the periphery of the first base part at a predetermined distance from the first base part, and of which the upper end is provided higher than the first embankment; and a first extension part which extends from the first base part to the first edge part, and of which the upper surface is positioned lower than the region where the first needle grooves are formed.

    IDENTIFICATION KEY GENERATION CIRCUIT BASED ON PROCESS VARIATION

    公开(公告)号:US20240370589A1

    公开(公告)日:2024-11-07

    申请号:US18580608

    申请日:2022-07-19

    Abstract: An identification key generation circuit using process deviation comprises a first semiconductor element portion and a second semiconductor element portion manufactured on a single semiconductor substrate and have different physical characteristics, an identification key generation portion generating an identification key using at least one of a difference in electrical characteristics of the first semiconductor element portion due to a process deviation occurring in the manufacturing process of the first semiconductor element portion and an identification key derivation portion determining the difference in electrical characteristic as a digital value, wherein the first semiconductor element portion is formed on the semiconductor substrate, and the second semiconductor element portion is formed on the upper portion of the first semiconductor element portion, and wherein the first semiconductor element portion and the second semiconductor element portion are connected to each other through at least one layer of via-holes, metal wiring, and contact hole layers.

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