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公开(公告)号：US20240212728A1
公开(公告)日：2024-06-27
申请号：US18145927
申请日：2022-12-23
发明人： Jeong Ho BANG , Hyeon Jae LEE , Wol Jin LEE , Ki Hyung RYOO , Kwang Rae CHO , Sun Byeong YOON
CPC分类号： G11C7/109 , G11C7/1087 , G11C7/12 , G11C8/18
摘要： A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.
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公开(公告)号：US11951571B2
公开(公告)日：2024-04-09
申请号：US18163338
申请日：2023-02-02
发明人： Cheng-Fu Yu , Kai-Jih Shih , Yi-Jung Liu
IPC分类号： B23K26/38 , B23K26/364 , H01L21/78 , H01L23/544
CPC分类号： B23K26/38 , B23K26/364 , H01L21/78 , H01L23/544
摘要： A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
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公开(公告)号：US11841722B2
公开(公告)日：2023-12-12
申请号：US17736119
申请日：2022-05-04
发明人： Shuenrun Seara Jian
摘要： A controlling circuit for a low-power low dropout regulator includes the low-power low dropout regulator, a current load detector and a bias current circuit. The low-power low dropout regulator has a first transmitting terminal and a second transmitting terminal. The first transmitting terminal is configured to transmit a first voltage, the second transmitting terminal is configured to transmit a second voltage, and the low-power low dropout regulator adjusts a voltage difference between the first voltage and the second voltage. The current load detector detects the first voltage and the second voltage, and compares the reference voltage with the second voltage to generate a detected signal. The bias current circuit generates a bias voltage and a reference current, and the low-power low dropout regulator dynamically adjust a bias current of the low-power low dropout regulator, so that the bias current is positively correlated with the reference current.
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公开(公告)号：US20230173615A1
公开(公告)日：2023-06-08
申请号：US18163338
申请日：2023-02-02
发明人： Cheng-Fu YU , Kai-Jih SHIH , Yi-Jung LIU
IPC分类号： B23K26/38 , H01L23/544 , B23K26/364 , H01L21/78
CPC分类号： B23K26/38 , B23K26/364 , H01L21/78 , H01L23/544
摘要： A method of forming a package structure includes an etching step, a laser step, a plating step and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. In the laser step, a plastic package material covering on each of the cutting streets is removed via a laser beam. In the plating step, a plurality of plating surfaces are disposed on a plurality of areas of the leadframe without the plastic package material. In the singulation step, the cutting streets of the leadframe are cut to form the package structure.
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5.发明公开公开(公告)号：US20230140988A1
公开(公告)日：2023-05-11
申请号：US17704152
申请日：2022-03-25
发明人： Shuenrun Seara JIAN
IPC分类号： G11C11/4074 , G05F1/56
CPC分类号： G11C11/4074 , G05F1/56
摘要： A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power network circuit has a first connecting point, a grid shape and a first unit network space. A second power network circuit has a second connecting point, another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space.
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公开(公告)号：US20220246501A1
公开(公告)日：2022-08-04
申请号：US17723536
申请日：2022-04-19
发明人： Cheng-Fu YU , Kai-Jih SHIH , Chi-Yi WU
IPC分类号： H01L23/495 , H01L23/31
摘要： A package structure includes a leadframe, a semiconductor die and a plastic package material. The leadframe includes a die pad and a plurality of leads. The leads are disposed on four peripheral regions of the die pad, and each of the leads includes a main body, at least one extending portion and a plurality of plating surfaces. The extending portion is connected to the main body, and the main body and the extending portion are integrally formed. The plating surfaces are disposed on the main body and the extending portion. The semiconductor die is disposed on the die pad of the leadframe. The plastic package material is disposed on the leadframe. The main body and the extending portion of each of the leads protrude a peripheral region of the plastic package material.
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公开(公告)号：US11378620B2
公开(公告)日：2022-07-05
申请号：US16944298
申请日：2020-07-31
发明人： Shou-Kang Fan , Lien-Sheng Yang
IPC分类号： G01R31/28
摘要： A method for detecting an abnormal die includes providing a wafer, determining the surrounding dies in accordance with a position of a target die on the wafer, calculating a difference between a value of an electrical characteristic of each of the surrounding dies and a value of an electrical characteristic of the target die to obtain the electrical characteristic deviations, ranking the absolute values of the electrical characteristic deviations to generate a ranking result, and determining the characteristic-related dies from the surrounding dies in accordance with the ranking result, determining a target-related area in accordance with the position of the target die, determining the target-related die from the characteristic-related dies in accordance with the target-related area and determining whether the target die is qualified in accordance with the target-related die.
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公开(公告)号：US20220020721A1
公开(公告)日：2022-01-20
申请号：US17488503
申请日：2021-09-29
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48
摘要： A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.
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公开(公告)号：US11195592B2
公开(公告)日：2021-12-07
申请号：US17009990
申请日：2020-09-02
发明人： PaiLu Dennis Wang , Lien-Sheng Yang
摘要： A memory inspecting method and a memory inspecting system are proposed. The memory inspecting system includes a testing machine and a computer system. The memory inspecting method includes: performing a first data retention time test on a plurality of memory chips to obtain a plurality of first qualified memory chips; performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips. Performing a statistical analysis step on the third qualified memory chips according to a first data retention time, a second data retention time and a third data retention time of each of the third qualified memory chips is for obtaining at least one final qualified memory chip.
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公开(公告)号：US20210296281A1
公开(公告)日：2021-09-23
申请号：US16824843
申请日：2020-03-20
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48
摘要： A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.
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