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公开(公告)号：US20070223484A1
公开(公告)日：2007-09-27
申请号：US11723394
申请日：2007-03-19
CPC分类号： H04J3/0664 , H04J3/0632 , H04J3/0682 , H04L12/403 , H04L45/10
摘要： A timing source is provided for sending timing information via a packet network. The source comprises a first clock for generating the timing information and a packet forming section for forming a sequence of packets. An output section in the form of a packet launch control section transmits the packets via the network as packet bursts, each of which comprises a plurality of packets with the intervals between consecutive packets of each burst being less than the intervals between consecutive packets. A time-stamping section inserts into each packet a transmission time derived from the timing information generated by the clock.
摘要翻译： 提供定时源，用于经由分组网络发送定时信息。 源包括用于产生定时信息的第一时钟和用于形成分组序列的分组形成部分。 分组发射控制部分形式的输出部分经由网络发送分组，作为分组突发，每个分组包括多个分组，每个分组的连续分组之间的间隔小于连续分组之间的间隔。 时间戳部分从时钟产生的定时信息中插入到每个分组中的传输时间。
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公开(公告)号：US07215665B2
公开(公告)日：2007-05-08
申请号：US10202925
申请日：2002-07-25
申请人： Stephen Paul Andrew
发明人： Stephen Paul Andrew
IPC分类号： H04L12/50
CPC分类号： H04Q11/0421
摘要： A time division multiplex switching apparatus is provided for switching channels from any number of input data streams, each of which may have any of a plurality of data rates, to any of a plurality of output data streams, each of which may likewise have any one of a plurality of data rates. An input block 1 comprises a respective input channel for each input stream. Each channel has a variable delay circuit. The outputs of the channels are supplied to a buffer memory 3 which stores data from the input channels in a first order and reads out the data in a second order according to the channel connections required. A controller 2 controls the variable delay circuits 12–14 independently of each other so as to align the data streams from the input channels irrespective of the input stream data rates. For example, the streams may be aligned such that the zeroth channel of a predetermined frame in the input streams appear consecutively at the outputs of the input channels.
摘要翻译： 提供了一种时分复用交换装置，用于将每个可以具有多个数据速率的任何数量的输入数据流的信道切换到多个输出数据流中的任何一个，其中每一个可以同样具有任何一个 的多个数据速率。 输入块1包括用于每个输入流的相应输入通道。 每个通道都有一个可变延迟电路。 通道的输出被提供给缓冲存储器3，该缓冲存储器3以一级顺序存储来自输入通道的数据，并根据所需的通道连接以二级读出数据。 控制器2彼此独立地控制可变延迟电路12-14，以便与输入流数据速率无关地对准来自输入通道的数据流。 例如，流可以对准，使得输入流中的预定帧的第零通道在输入通道的输出处连续出现。
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公开(公告)号：US07038296B2
公开(公告)日：2006-05-02
申请号：US10774032
申请日：2004-02-06
申请人： Peter Graham Laws
发明人： Peter Graham Laws
IPC分类号： H01L29/00
CPC分类号： H01G4/012 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An electrical component structure (14) comprises a plurality of overlying substantially parallel layers (15, 16). Each layer (15, 16) provides a lattice (17, 20) comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands (18, 22) are located in windows of the lattices (17, 20), the conductive islands being electrically isolated from the tracks. The lattice (17, 20) of each layer (15, 16) is electrically connected to the conductive islands (22, 18) of the other adjacent layer (16, 15).
摘要翻译： 电气部件结构（14）包括多个重叠的大致平行的层（15,16）。 每个层（15,16）提供格子（17,20），其包括基本上与第二组导电轨道正交并电连接的第一组导电轨道。 导电岛（18,22）位于格子（17,20）的窗口中，导电岛与轨道电隔离。 每个层（15,16）的格子（17,20）电连接到另一相邻层（16,15）的导电岛（22,18）。
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公开(公告)号：US06968173B2
公开(公告)日：2005-11-22
申请号：US10195586
申请日：2002-07-15
申请人： Nicholas Paul Cowley
发明人： Nicholas Paul Cowley
CPC分类号： H03L7/0805 , H03J3/08 , H03L7/099
摘要： A tuner comprises a frequency changer which converts an input signal to a predetermined fixed intermediate frequency. The frequency changer is followed by an IF filter having a filter parameter, such as center frequency, which is electronically adjustable. A controller adjusts the adjustable filter characteristic so as to achieve a predetermined desired filtering performance, such as ensuring that the filter center frequency corresponds to the desired intermediate frequency. The controller comprises a local oscillator having the same type of tuned circuit as the IF filter. A phase locked loop compares the local oscillator frequency with a reference frequency and controls the tuned circuits of the IF filter and the local oscillator.
摘要翻译： 调谐器包括将输入信号转换为预定的固定中频的变频器。 变频器之后是具有滤波器参数（例如中心频率）的IF滤波器，其可电子调节。 控制器调节可调滤波器特性，以便实现预定的期望的滤波性能，例如确保滤波器中心频率对应于期望的中频。 控制器包括具有与IF滤波器相同类型的调谐电路的本地振荡器。 锁相环将本地振荡器频率与参考频率进行比较，并控制中频滤波器和本地振荡器的调谐电路。
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公开(公告)号：US06844788B2
公开(公告)日：2005-01-18
申请号：US10267905
申请日：2002-10-09
CPC分类号： H03F1/3282 , H03F1/0205 , H03F1/32 , H03F1/3247 , H03F2201/3233
摘要： A polar loop transmitter circuit arrangement includes a circuit input, a circuit output, a controllable signal source, a modulator connected between the signal source and the output, a first amplifier having its input connected to the circuit input, a second amplifier having its input connected to the circuit output, and a comparator. Each amplifier preferably includes respective amplitude detector and signal modifier portions connected in series between their respective inputs and outputs. An output of each of the amplifiers is connected to a respective input of the comparator, and an output of the comparator is connected to a control input of the modulator. The amplifiers may each be characterized by transfer functions that are generally logarithmic. Each amplifier's signal modifier portion may further include an analog-to-digital converter, a digital signal modifier, and a digital-to-analog converter. Additional signal mixer and/or phase comparison elements may also be incorporated into select embodiments of the subject polar loop transmitter technology.
摘要翻译： 极环回路发射器电路装置包括电路输入端，电路输出端，可控信号源，连接在信号源与输出端之间的调制器，第一放大器，其输入端连接到电路输入端;第二放大器，其输入端连接 到电路输出，以及一个比较器。 每个放大器优选地包括在它们各自的输入和输出之间串联连接的相应的振幅检测器和信号修正器部分。 每个放大器的输出端连接到比较器的相应输入端，比较器的输出端连接到调制器的控制输入端。 放大器的每个都可以通过通常为对数的传递函数来表征。 每个放大器的信号修改器部分还可以包括模数转换器，数字信号修改器和数模转换器。 附加的信号混合器和/或相位比较元件也可以并入目标极环发射机技术的选择实施例中。
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公开(公告)号：US20040003311A1
公开(公告)日：2004-01-01
申请号：US10395025
申请日：2003-03-21
发明人： Marcus Richard Jones
IPC分类号： G06F001/32 , G06F013/00
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/325 , H04W52/0241 , Y02D10/128 , Y02D70/142 , Y02D70/144
摘要： A communications system comprises a PDA and a Bluetooth peripheral device. The Bluetooth peripheral device is connected to the PDA by a data channel. The Bluetooth peripheral device enables the PDA to communicate with remote data networks using the Bluetooth wireless protocol. The system is configured to operate according to an algorithm that enables the Bluetooth peripheral device to enter an ultra-low power mode in which a receiver associated with data transfer can be disabled when no data is required to be transmitted. Data loss is prevented through the use of a hardware handshake mechanism that stops the PDA from sending data while the Bluetooth peripheral device is in the low power mode. Latency in the PDA responding to a change in handshake signals is provided.
摘要翻译： 通信系统包括PDA和蓝牙外围设备。 蓝牙外围设备通过数据通道连接到PDA。 蓝牙外围设备使PDA能够使用蓝牙无线协议与远程数据网络进行通信。 该系统被配置为根据使得蓝牙外围设备进入超低功率模式的算法来操作，其中当不需要发送数据时，可以禁用与数据传输相关联的接收器。 通过使用硬件握手机制防止数据丢失，该机制在蓝牙外围设备处于低功耗模式时停止PDA发送数据。 提供了响应于握手信号改变的PDA中的延迟。
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公开(公告)号：US20030231127A1
公开(公告)日：2003-12-18
申请号：US10458767
申请日：2003-06-12
发明人： Marcus Richard Jones
IPC分类号： H03M001/66
摘要： A data processing system is disclosed including a data processor for operating on data samples received from a data source, a digital to analog converter arranged to receive the data samples from the data processor and to convert the received data samples into an analog signal, and a controller arranged to monitor the magnitude of the data samples received from the data source and disable one or both of the data processor means and the digital to analog converter when the magnitude of one or more received data samples falls within a predetermined magnitude range. Such a system is able to operate in a low-power mode that may be advantageous for battery-powered device or other applications where power conservation is important.
摘要翻译： 公开了一种数据处理系统，其包括用于对从数据源接收的数据样本进行操作的数据处理器，被配置为从数据处理器接收数据样本并将接收到的数据样本转换为模拟信号的数模转换器，以及 控制器被布置为当一个或多个接收的数据样本的幅度落在预定的幅度范围内时，监视从数据源接收的数据样本的大小并禁用数据处理器装置和数模转换器中的一个或两个。 这样的系统能够以低功率模式运行，这对于电池供电的设备或其中节能很重要的其它应用来说可能是有利的。
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公开(公告)号：US20030200490A1
公开(公告)日：2003-10-23
申请号：US10372640
申请日：2003-02-21
发明人： Alistair Goudie
IPC分类号： G06F011/00
CPC分类号： H04L7/033 , H04L7/0083 , H04L7/042
摘要： A data and clock recovery circuit is provided for generating a recovered version of a transmitted data stream. The data and clock recovery circuit comprises three main circuit modules, namely a data recovery circuit, a clock recovery circuit, and a detector circuit. The data recovery circuit is arranged to receive a data stream, and to generate therefrom an estimate of the signal levels for each bit-period of the originally transmitted data stream. The estimates of the signal levels are stored within the data recovery circuit and are sampled by the clock recovery circuit so that the original data stream is recovered. The data recovery circuit is also arranged to generate a so-called nullword metricnull which is a quality factor representing the accuracy of the estimated signal levels. The clock recovery circuit is arranged to use both the received data stream, and the word metric generated in the data recovery circuit, to determine whether or not the current sampling time is optimal. If not, the current sampling time is adjusted so that it moves towards an nullidealnull sampling time. The detector circuit, which may correspond to a correlator in some embodiments, is arranged to determine when the start of a new data stream is received.
摘要翻译： 提供了一种数据和时钟恢复电路，用于产生已发送数据流的恢复版本。 数据和时钟恢复电路包括三个主要电路模块，即数据恢复电路，时钟恢复电路和检测器电路。 数据恢复电路被布置为接收数据流，并且从其生成原始传输的数据流的每个位周期的信号电平的估计。 信号电平的估计被存储在数据恢复电路内，并被时钟恢复电路采样，从而恢复原始数据流。 数据恢复电路还被布置成产生所谓的“字度量”，其是表示估计信号电平精度的品质因子。 时钟恢复电路被设置为使用接收的数据流和在数据恢复电路中生成的字度量来确定当前采样时间是否是最佳的。 如果不是，则调整当前采样时间，使其朝“理想”采样时间移动。 在一些实施例中，可以对应于相关器的检测器电路被布置成确定何时接收到新数据流的开始。
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公开(公告)号：US20030122215A1
公开(公告)日：2003-07-03
申请号：US09954691
申请日：2001-09-12
发明人： Martin Clive Wilson
IPC分类号： H01L029/00
CPC分类号： H01L21/76264 , H01L21/76283 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate (11) having an insulating layer (12) formed on a surface thereof, and a silicon layer (13) located on a surface of the insulating layer. A trench (14) extends from a surface of the silicon layer (13) through the insulating layer (12) and into the substrate (11). An insulating liner (14a) is located on the side walls and the base of the trench (14), and an in-fill (14b) of thermally-conductive material is formed within the insulating liner. The insulating liner (14a), the in-fill material (14b) and the distance over which the trench 14) extends into the substrate (11) are such as to promote flow of heat from the silicon layer (13) to the substrate.
摘要翻译： 半导体器件包括在其表面上形成有绝缘层（12）的基板（11）和位于绝缘层表面上的硅层（13）。 沟槽（14）从硅层（13）的表面延伸穿过绝缘层（12）并进入衬底（11）。 绝缘衬垫（14a）位于沟槽（14）的侧壁和底座上，并且在绝缘衬里内形成有导热材料的填充物（14b）。 绝缘衬垫（14a），填充材料（14b）以及沟槽14延伸到衬底11中的距离）以促进热量从硅层（13）流到衬底。
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公开(公告)号：US20030073419A1
公开(公告)日：2003-04-17
申请号：US10267904
申请日：2002-10-09
IPC分类号： H04B001/04 , H04B017/00 , H03C001/62 , H01Q011/12
CPC分类号： H03G3/3036 , H03C5/00
摘要： A polar loop transmitter circuit arrangement comprises a circuit input, a circuit output, a controllable signal source, a modulator connected between the signal source and the circuit output, a first signal-amplitude-sensitive element having its input connected to the circuit input, a second signal-amplitude-sensitive element having its input connected to the circuit output, a comparator, and at least one controllable attenuator. An output of each of the signal-amplitude-sensitive elements is connected to a respective input of the comparator, and an output of the comparator is connected to a control input of the modulator. Another controllable attenuator may also be connected between the circuit output and an input of the second signal-amplitude-sensitive element. The signal-amplitude-sensitive elements may correspond to amplitude detectors in some embodiments of the technology, and to logarithmic amplifiers in other embodiments. Additional features for comparing the respective phases of the circuit input and the circuit output may be utilized to control the signal source.
摘要翻译： 极环回路发射器电路装置包括电路输入，电路输出，可控信号源，连接在信号源和电路输出之间的调制器，具有连接到电路输入的输入的第一信号幅度敏感元件， 其输入端连接到电路输出的第二信号幅度敏感元件，比较器和至少一个可控衰减器。 每个信号幅度敏感元件的输出连接到比较器的相应输入，比较器的输出端连接到调制器的控制输入。 另一可控衰减器也可以连接在电路输出端和第二信号幅度敏感元件的输入端之间。 信号幅度敏感元件可以对应于本技术的一些实施例中的幅度检测器，在其他实施例中可对应于对数放大器。 可以利用用于比较电路输入和电路输出的各个相位的附加特征来控制信号源。
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