公开(公告)号：US12301789B2

公开(公告)日：2025-05-13

申请号：US17560533

申请日：2021-12-23

Applicant: ATI Technologies ULC

Inventor： Ahmed M. Abdelkhalek ,  Ihab M. A. Amer ,  Khaled Mammou

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/14 ,  H04N19/172

Abstract: Disclosed herein is a region-based reference management system using in video frame encoding. Source content, such as video game streaming or remote desktop sharing, that includes scene changes or significant instantaneous changes in a region from one frame to the next can present encoding challenges. Techniques disclosed herein use hints about changes in regional frame content, dissect frame content into regions, and associate the dissected regions with stored reference frame data using the hints and information about the regions to more efficiently encode frames.

公开(公告)号：US12293485B2

公开(公告)日：2025-05-06

申请号：US17976192

申请日：2022-10-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Steven Tovey ,  Jimmy Stefan Petersson ,  Thomas Arcila ,  Zhuo Chen ,  Stephan Hodes ,  Colin Riley ,  Sylvain Daniel Julien Meunier

IPC: G06T3/4053 ,  G06T7/246

Abstract: A first frame of a video stream rendered at a first resolution is obtained. A second frame of the video stream upscaled to a second higher resolution is also obtained. The first plurality of pixels is upscaled to the second resolution. The upsampling generates upsampled color data for the upsampled first plurality of pixels. The upsampled color data is accumulated with a second set of color data associated with a second plurality of pixels defining the second frame to generate final color data for the upsampled first plurality of pixels. Color data of the second set of color data associated with a pixel lock contributes more to the final color data than corresponding color data of the upsampled color data. The upsampled first plurality of pixels is stored with the final color data as an upscaled frame representing the first frame at the second resolution.

公开(公告)号：US12277915B2

公开(公告)日：2025-04-15

申请号：US18108251

申请日：2023-02-10

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. Glen

IPC: G09G5/00 ,  G09G5/36

Abstract: A display system supports variable refresh rates that include a plurality of refresh rates. A source such as a graphics processing unit (GPU) provides frames to the display system at a selected one of the refresh rates. The refresh rates are factored into a corresponding plurality of prime factors. A plurality of numbers of lines per frame in frames provided at the plurality of refresh rates is determined based on one or more ratios of the plurality of refresh rates, the plurality of prime factors, and a line rate for providing frames to the display system at the plurality of refresh rates. The source then selectively provides frames to the display system at one refresh rate of the plurality of refresh rates using the same line rate regardless of which refresh rate is chosen. Furthermore, the number of lines per frame is an integer for frames provided at the refresh rates.

公开(公告)号：US12271515B1

公开(公告)日：2025-04-08

申请号：US18395065

申请日：2023-12-22

Applicant: ATI Technologies ULC

Inventor： Michael Yee

IPC: G06F3/01 ,  G06T1/20 ,  G06T11/00

Abstract: The disclosed device can receive a biosignal and, using user input predictions based on the biosignal, pre-render a display frame. The device can also subsequently receive a user input, output the pre-rendered display frame based on the user input confirming the user input predictions and flush the pre-rendered display frame otherwise. The device can also modulate computing performance and power based on computing demands predicted from the biosignal. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250110930A1

公开(公告)日：2025-04-03

申请号：US18478895

申请日：2023-09-29

Applicant: ATI Technologies ULC

Inventor： Yinan Jiang ,  Dmytro Chenchykov ,  Shaoyun Liu ,  Vignesh Chander

IPC: G06F16/21

Abstract: A computer-implemented method for ensuring processing unit hardware state integrity in live migration can include participating as a source, by a processing unit, in a live migration procedure by injecting, into a live migration data package containing a state of the processing unit, a signature verifying the state. The method can additionally include participating as a target, by the processing unit, in an additional live migration procedure migrating an additional live migration data package containing an additional state of an additional processing unit by performing an integrity check based on an additional signature, in the additional live migration data package, verifying the additional state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12265908B2

公开(公告)日：2025-04-01

申请号：US17008360

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Benjamin Thomas Sander ,  Swapnil Sakharshete ,  Ashish Panday

IPC: G06N3/08 ,  G06F12/121

Abstract: Systems, apparatuses, and methods for achieving higher cache hit rates for machine learning models are disclosed. When a processor executes a given layer of a machine learning model, the processor generates and stores activation data in a cache subsystem a forward or reverse manner. Typically, the entirety of the activation data does not fit in the cache subsystem. The processor records the order in which activation data is generated for the given layer. Next, when the processor initiates execution of a subsequent layer of the machine learning model, the processor processes the previous layer's activation data in a reverse order from how the activation data was generated. In this way, the processor alternates how the layers of the machine learning model process data by either starting from the front end or starting from the back end of the array.

公开(公告)号：US20250098326A1

公开(公告)日：2025-03-20

申请号：US18369451

申请日：2023-09-18

Applicant: ATI Technologies ULC

Inventor： Ioan CORDOS

IPC: H01L27/02 ,  H01L27/118

Abstract: Embodiments herein describe identifying voltage potentials in separate cells that can be combined so that a dummy gate between or in the cells can be removed. For example, some combinational logic cells such as XOR gates, XNOR gates, and half-adders are formed from coupling two combinational cells in sequence. Typically, a dummy gate is placed between those cells since they have different voltage potentials. However, if the cells have the same voltage potentials, then the dummy gate can be removed and the cells can overlap by sharing a net. This can reduce the overall size of the cell.

公开(公告)号：US20250085875A1

公开(公告)日：2025-03-13

申请号：US18745994

申请日：2024-06-17

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael LITT ,  Yubin YAO

IPC: G06F3/06

Abstract: Examples herein describe techniques for directed refresh management (DRFM) address capture in high-bandwidth memory (HBM). Some examples are based on an activate command that includes a DRFM flag, including examples in which the activate command is received and processed while a bank is open, examples in which an address of a target row is captured without opening the corresponding bank, and examples in which the address of a target row is captured based further on a mode registers. Other examples are based on a precharge command that includes a DRFM flag.

公开(公告)号：US20250077379A1

公开(公告)日：2025-03-06

申请号：US18460678

申请日：2023-09-04

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Guennadi Riguer ,  Christopher J. Brennan

IPC: G06F11/32 ,  G06F11/30 ,  G06F11/34 ,  G06T11/20

Abstract: Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.

公开(公告)号：US12238295B2

公开(公告)日：2025-02-25

申请号：US17236910

申请日：2021-04-21

Applicant: ATI Technologies ULC

Inventor： Mehdi Saeedi ,  Boris Ivanovic

IPC: H04N19/14 ,  H04N19/176 ,  H04N19/513

Abstract: Systems, apparatuses, and methods for implementing spatial block-level pixel activity extraction optimization leveraging motion vectors are disclosed. Control logic coupled to an encoder generates block-level pixel activity metrics for a new frame based on the previously calculated block-level pixel activity data from a reference frame. A cost is calculated for each block of a new frame with respect to a corresponding block of the reference frame. If the cost is less than a first threshold, then the control logic generates an estimate of a pixel activity metric for the block which is equal to a previously calculated pixel activity metric for a corresponding block of the reference frame. If the cost is greater than the first threshold but less than a second threshold, an estimate of the pixel activity metric is generated by extrapolating from the previously calculated pixel activity metric.