公开(公告)号：US4399507A

公开(公告)日：1983-08-16

申请号：US280417

申请日：1981-06-30

申请人： Michael R. Cosgrove, deceased ,  Alexander H. Frey, Jr. ,  Kenneth A. Moore ,  Abraham Peled ,  Frederic N. Ris ,  William W. Sproul, III

发明人： Michael R. Cosgrove, deceased ,  Alexander H. Frey, Jr. ,  Kenneth A. Moore ,  Abraham Peled ,  Frederic N. Ris ,  William W. Sproul, III

IPC分类号： G06F9/38 ,  G06F9/42 ,  G06F9/28

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3889 ,  G06F9/4426

摘要： An instruction pipeline for a data processor is disclosed, in which instruction execution is carried out in a sequence of phases which include fetching the instruction from an instruction storage, computing a data storage address from the fetched instruction, accessing the data storage at the computed address to obtain a datum operand, and then carrying out the logical or arithmetic operation on the accessed datum in accordance with the fetched instruction. Branch and stack instructions and return instructions are accommodated by providing a return address stack in the data storage, which stores the next instruction store address to be returned to after a return operation has been completed. Since the instruction address stack in the data storage cannot be directly accessed by the instruction fetching stage of the pipeline until several instruction execution phases have transpired, without degrading the performance of the pipeline, a stack register is provided in the instruction fetch stage of the pipeline which contains a duplicate of the instruction store address presently residing at the top of the instruction address stack. Then when a return instruction is encountered in the instruction fetch stage, the address of the next instruction to be returned to in the instruction storage is immediately available without interrupting the flow in the pipeline. A stack pointer in a stage of the pipeline between the instruction fetch stage and the data store access stage, then takes advantage of unused instruction phases in the pipeline, to cause the data store access stage to read the next available instruction store address from the instruction address stack therein and load it into the stack register in preparation for the next return instruction. Thus, the data storage and instruction stacking function can be shared in the same data storage device which is accessed by an intermediate stage in the multiple phase instruction pipeline without degrading the performance of the pipeline.

公开(公告)号：US3993890A

公开(公告)日：1976-11-23

申请号：US618307

申请日：1975-09-29

申请人： Abraham Peled ,  Bede Liu

发明人： Abraham Peled ,  Bede Liu

IPC分类号： H03H17/04 ,  G06F15/20 ,  G06F7/38

CPC分类号： H03H17/0405

摘要： A combinatorial digital filter apparatus utilizing a second order filter in which bits are processed simultaneously rather than serially.

摘要翻译： 一种利用二阶滤波器的组合数字滤波器装置，其中位同时处理而不是串行处理。