公开(公告)号：US20130190942A1

公开(公告)日：2013-07-25

申请号：US13356227

申请日：2012-01-23

Applicant: Balakrishna Pamulaparthy ,  Manish Kumar Sharma ,  Aditya Gupta

Inventor： Balakrishna Pamulaparthy ,  Manish Kumar Sharma ,  Aditya Gupta

IPC: G06F1/32

CPC classification number: G01D4/002 ,  Y02B90/241 ,  Y02B90/244 ,  Y04S20/32 ,  Y04S20/327

Abstract: Embodiments of the invention can provide systems and methods for controlling the load of demand response metering devices. According to one embodiment of the invention, a system can be provided. The system can be operable to receive a load limit, store the load limit, determine a load demand of a location, provide an alarm when the load demand is greater than the load limit, and restrict electricity to the location when the load demand remains greater than the load limit for a predetermined amount of time.

Abstract translation: 本发明的实施例可以提供用于控制需求响应计量装置的负载的系统和方法。 根据本发明的一个实施例，可以提供一种系统。 该系统可以操作以接收负载限制，存储负载极限，确定位置的负载需求，当负载需求大于负载限制时提供报警，并且当负载需求保持较大时将电力限制在该位置 超过预定量的时间的负载限制。

公开(公告)号：US20080082707A1

公开(公告)日：2008-04-03

申请号：US11906059

申请日：2007-09-28

Applicant: Shail Aditya Gupta ,  David John Simpson

Inventor： Shail Aditya Gupta ,  David John Simpson

IPC: G06F13/18

CPC classification number: G06F13/364 ,  G06F13/1615

Abstract: A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.

Abstract translation: 本文公开了一种用于总线控制器的方法和装置，该总线控制器支持灵活的总线协议，该协议处理流水线的可变等待时间总线事务，同时以非阻塞的方式保持事务的点对点（P2P）FIFO排序。 在一个实施例中，该装置包括总线控制器，用于在总线的第一输入端口处接收多个总线事务。 总线控制器被配置为以流水线方式处理多个总线事务，即使当多个总线事务采取可变数目的周期完成时，也保持多个总线事务的P2P FIFO排序。

公开(公告)号：US07107199B2

公开(公告)日：2006-09-12

申请号：US10284932

申请日：2002-10-31

Applicant: Robert S. Schreiber ,  Shail Aditya Gupta ,  Vinod K. Kathail ,  Santosh George Abraham ,  Bantwal Ramakrishna Rau

Inventor： Robert S. Schreiber ,  Shail Aditya Gupta ,  Vinod K. Kathail ,  Santosh George Abraham ,  Bantwal Ramakrishna Rau

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.

Abstract translation: 一种设计流水线的方法包括以下步骤：接受以标准编程语言表达的任务过程，所述任务过程包括一系列计算步骤; 接受管道的性能要求; 以及自动创建所述流水线的硬件描述，所述流水线包括多个互连的处理器级，每个处理器级用于执行相应的一个计算步骤，所述流水线具有与流水线的性能要求一致的特性。

公开(公告)号：US20060113566A1

公开(公告)日：2006-06-01

申请号：US11331630

申请日：2006-01-13

Applicant: Oleh Krutko ,  Kezhou Xie ,  Mohsen Shokrani ,  Aditya Gupta ,  Boris Gedzberg

Inventor： Oleh Krutko ,  Kezhou Xie ,  Mohsen Shokrani ,  Aditya Gupta ,  Boris Gedzberg

IPC: H01L31/109

CPC classification number: H01L27/0623 ,  H01L27/0605

Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.

Abstract translation: 公开了用于制造HBT / FET集成对的方法和系统。 一个优选实施例包括一种制造基于GaAs的HBT和FET的集成对的方法。 该方法包括以下步骤：在半绝缘GaAs衬底上生长用于制造FET的第一组外延层; 制造用作FET的盖层的高掺杂厚GaAs层和用于HBT的子集电极层; 以及制造用于制造HBT的第二组外延层。

公开(公告)号：US07000137B2

公开(公告)日：2006-02-14

申请号：US10266830

申请日：2002-10-07

Applicant: Mukund Sivaraman ,  Shail Aditya Gupta

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta

IPC: G06F1/04 ,  G06F9/45

CPC classification number: G06F17/5031

Abstract: A method for performing a global timing analysis of a proposed digital circuit comprising receiving timing models and the proposed digital circuit; determining at least one mode of circuit operation of the proposed digital circuit; deriving a sub-circuit corresponding to each of at least one mode of circuit operation; performing timing analysis on each of the sub-circuits derived corresponding to each of the modes; and combining the timing analysis results for all of the modes to determine an overall maximum circuit delay.

Abstract translation: 一种用于执行所提出的数字电路的全局时序分析的方法，包括接收定时模型和所提出的数字电路; 确定所提出的数字电路的至少一种电路操作模式; 导出与至少一种电路操作模式中的每一个对应的子电路; 对与每种模式对应的每个子电路执行定时分析; 并组合所有模式的定时分析结果以确定总体最大电路延迟。

公开(公告)号：US06853970B1

公开(公告)日：2005-02-08

申请号：US09378596

申请日：1999-08-20

Applicant: Shail Aditya Gupta ,  B. Ramakrishna Rau

Inventor： Shail Aditya Gupta ,  B. Ramakrishna Rau

IPC: G06F9/44 ,  G06F13/10 ,  G06F13/12 ,  G06F17/50

CPC classification number: G06F17/5045

Abstract: A method for the automatic design of processor datapaths operates on an abstract input specification of desired processor operations and their instruction level parallelism and synthesizes a datapath design in machine readable form. A datapath synthesizer automatically designs and synthesizes the processor datapath including the number and types of functional units, the number of read/write ports of the various register files, and the exact connectivity between the register files and the functional units. The heuristics used in the implementation maximize resource sharing and minimize the overall cost in by customizing and sharing functional units and minimizing the number of read/write ports on the register files subject to the specified ILP among operations.

Abstract translation: 一种用于自动设计处理器数据路径的方法是在所需处理器操作的抽象输入规范及其指令级并行性的基础上进行操作，并以机器可读形式合成数据路径设计。 数据路径合成器自动设计和合成处理器数据路径，包括功能单元的数量和类型，各种寄存器文件的读/写端口数，以及寄存器文件和功能单元之间的确切连接。 实现中使用的启发式方法最大化资源共享，并通过定制和共享功能单元并最大限度地减少受操作中指定ILP的寄存器文件的读/写端口数量，从而最大限度地降低总体成本。

公开(公告)号：US06766445B2

公开(公告)日：2004-07-20

申请号：US09816851

申请日：2001-03-23

Applicant: Michael Steven Schlansker ,  Vinod Kumar Kathail ,  Shail Aditya Gupta

Inventor： Michael Steven Schlansker ,  Vinod Kumar Kathail ,  Shail Aditya Gupta

IPC: G06F940

CPC classification number: G06F9/3885 ,  G06F9/3001 ,  G06F9/30134 ,  G06F9/325

Abstract: A computational unit for use in loop computations. The computational unit includes a function unit, a plurality of phase lines, and a storage register. The computational unit is programmed to initiate one iteration of the loop every II cycles. Each function unit has a result output for outputting one computational result each cycle. There is one phase line corresponding to each of the II cycles. The storage register includes a linear connected array of shift cells having a first shift cell. Each shift cell has an input port, an output port, a shift control port, and an OR gate. Each shift cell receives the value to be stored in the shift cell on the input port, the stored value being stored in response to a control signal on the shift control port. The OR gate has an output connected to the shift enable port and one input for each cycle on which that shift cell is to receive the control signal, that input being connected to the phase line corresponding to that cycle. The input port of the first shift cell is connected to the result output. A plurality of such computational units can be connected together to form a loop accelerator. The accelerator includes a cross-connect circuit for coupling at least one shift cell output of one of the computational units to an input of a function unit of another of the computational units on a selected one of the II cycles.

Abstract translation: 用于循环计算的计算单元。 计算单元包括功能单元，多个相位线以及存储寄存器。 计算单元被编程为每二个周期启动循环的一次迭代。 每个功能单元具有用于每个周期输出一个计算结果的结果输出。 存在对应于每个II周期的一相线。 存储寄存器包括具有第一移位单元的移位单元的线性连接阵列。 每个移位单元具有输入端口，输出端口，移位控制端口和或门。 每个移位单元接收要存储在输入端口上的移位单元中的值，响应于移位控制端口上的控制信号存储存储的值。 或门具有连接到移位使能端口的输出端和用于接收控制信号的移位单元的每个周期的一个输入，该输入端连接到与该周期对应的相位线。 第一移位单元的输入端口连接到结果输出。 多个这样的计算单元可以连接在一起以形成环路加速器。 加速器包括交叉连接电路，用于将所述计算单元中的一个的至少一个移位单元输出耦合到所述II个周期中的所选择的一个计算单元的功能单元的输入。

公开(公告)号：US06966043B2

公开(公告)日：2005-11-15

申请号：US10266831

申请日：2002-10-07

Applicant: Mukund Sivaraman ,  Shail Aditya Gupta

Inventor： Mukund Sivaraman ,  Shail Aditya Gupta

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.

Abstract translation: 一种在电路设计过程中考虑电路定时要求的方法，包括接收时钟周期时间约束; 从宏单元库接收硬件资源的延迟特性; 接收操作，与所述操作相关联的替代时钟周期以及与所述操作相关联的备选硬件资源; 以及使用所述程序图的硬件结构表示来确定所述接收的备选方案相对于时序约束的有效性。

公开(公告)号：US20050184310A1

公开(公告)日：2005-08-25

申请号：US10783830

申请日：2004-02-20

Applicant: Oleh Krutko ,  Kezhou Xie ,  Mohsen Shokrani ,  Aditya Gupta ,  Boris Gedzberg

Inventor： Oleh Krutko ,  Kezhou Xie ,  Mohsen Shokrani ,  Aditya Gupta ,  Boris Gedzberg

IPC: H01L27/06 ,  H01L29/739

CPC classification number: H01L27/0623 ,  H01L27/0605

Abstract: Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.

Abstract translation: 公开了用于制造HBT / FET集成对的方法和系统。 一个优选实施例包括一种制造基于GaAs的HBT和FET的集成对的方法。 该方法包括以下步骤：在半绝缘GaAs衬底上生长用于制造FET的第一组外延层; 制造用作FET的盖层的高掺杂厚GaAs层和用于HBT的子集电极层; 以及制造用于制造HBT的第二组外延层。

公开(公告)号：US06629312B1

公开(公告)日：2003-09-30

申请号：US09378601

申请日：1999-08-20

Applicant: Shail Aditya Gupta

Inventor： Shail Aditya Gupta

IPC: G06F945

CPC classification number: G06F8/47

Abstract: An MDES extractor automatically extracts a machine description (MDES) for re-targeting a compiler from a structural representation of a datapath of an explicitly parallel instruction computing (EPIC) processor. The datapath is a machine readable data structure that specifies the functional unit instances and an interconnect of the functional unit instances to registers. The MDES extractor structurally traverses the interconnect, identifying resource conflicts among the operations in the processor's opcode repertoire. Latencies and internal resources of the opcodes associated with the functional unit instances are obtained from a macrocell library. The MDES extractor then identifies external resource conflicts by preparing reservation tables for the functional units.

Abstract translation: MDES提取器自动提取机器描述（MDES），用于从显式并行指令计算（EPIC）处理器的数据路径的结构表示重新定位编译器。 数据路径是一种机器可读数据结构，用于指定功能单元实例和功能单元实例与寄存器的互连。 MDES提取器在结构上遍历互连，识别处理器操作码中所有操作之间的资源冲突。 从宏单元库获得与功能单元实例相关联的操作码的延迟和内部资源。 然后，MDES提取器通过准备功能单元的预留表来识别外部资源冲突。