公开(公告)号：US20090265673A1

公开(公告)日：2009-10-22

申请号：US12105299

申请日：2008-04-18

申请人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

发明人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

摘要翻译： 提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。 物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。 采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。 可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。

公开(公告)号：US07941780B2

公开(公告)日：2011-05-10

申请号：US12105299

申请日：2008-04-18

申请人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

发明人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

摘要翻译： 提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。 物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。 采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。 可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。