公开(公告)号：US07337420B2

公开(公告)日：2008-02-26

申请号：US11193711

申请日：2005-07-29

申请人： Dureseti Chidambarrao ,  Donald L. Jordan ,  Judith H. McCullen ,  David M. Onsongo ,  Tina Wagner ,  Richard Q. Williams

发明人： Dureseti Chidambarrao ,  Donald L. Jordan ,  Judith H. McCullen ,  David M. Onsongo ,  Tina Wagner ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

摘要翻译： 用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。 布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

公开(公告)号：US07941780B2

公开(公告)日：2011-05-10

申请号：US12105299

申请日：2008-04-18

申请人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

发明人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

摘要翻译： 提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。 物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。 采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。 可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。

公开(公告)号：US06869542B2

公开(公告)日：2005-03-22

申请号：US10249047

申请日：2003-03-12

申请人： Sadanand V. Desphande ,  David Dobuzinsky ,  Arpan P. Mahorowala ,  Tina Wagner ,  Richard Wise

发明人： Sadanand V. Desphande ,  David Dobuzinsky ,  Arpan P. Mahorowala ,  Tina Wagner ,  Richard Wise

IPC分类号： B44C1/22 ,  H01L21/00 ,  H01L21/027 ,  H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0276 ,  H01L21/31116

摘要： Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (−20 to 60°).

摘要翻译： 在形成在基板上的电介质层中形成开口，包括在电介质层上沉积由耐蚀刻材料构成的硬掩模， 氧化硅。 使用光刻胶掩模露出硬掩模。 使用氟碳等离子体通过窗口蚀刻以形成通过硬掩模的开口。 然后蚀刻穿过硬掩模开口以对介电层进行图案化。 硬掩模包括具有结构式R：C：H或R：C：H：X的RCH / RCHX材料，其中R选自Si，Ge，B，Sn，Fe，Ti和X选自O， N，S和F.等离子体蚀刻工艺使用a）包含N 2的气体混合物; 碳氟化合物（CHF 3，C 4 F 8，C 4 F 6，CF 4，CH 2 F 2，CH 3 F）; 氧化剂（O 2，CO 2）和稀有稀释剂（Ar，He）; b）高直流偏置（晶片上的500-3000伏偏压）; 3）中压（20-100mT;和d）中等温度（-20至60°）。

公开(公告)号：US06660664B1

公开(公告)日：2003-12-09

申请号：US09541091

申请日：2000-03-31

申请人： James W. Adkisson ,  Arne W. Ballantine ,  Matthew D. Gallagher ,  Peter J. Geiss ,  Jeffrey D. Gilbert ,  Shwu-Jen Jeng ,  Donna K. Johnson ,  Robb A. Johnson ,  Glen L. Miles ,  Kirk D. Peterson ,  James J. Toomey ,  Tina Wagner

发明人： James W. Adkisson ,  Arne W. Ballantine ,  Matthew D. Gallagher ,  Peter J. Geiss ,  Jeffrey D. Gilbert ,  Shwu-Jen Jeng ,  Donna K. Johnson ,  Robb A. Johnson ,  Glen L. Miles ,  Kirk D. Peterson ,  James J. Toomey ,  Tina Wagner

IPC分类号： H01L2131

CPC分类号： H01L28/20 ,  H01L21/3185

摘要： A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

摘要翻译： 一种在半导体衬底上形成氮化物膜的方法，包括将衬底的表面暴露于快速热处理以形成氮化物膜。

公开(公告)号：US6090722A

公开(公告)日：2000-07-18

申请号：US225595

申请日：1999-01-06

申请人： Michael Armacost ,  Sandra G. Malhotra ,  Tina Wagner ,  Richard Wise

发明人： Michael Armacost ,  Sandra G. Malhotra ,  Tina Wagner ,  Richard Wise

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/60 ,  H01L29/78 ,  H01L21/469

CPC分类号： H01L21/76829 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76897 ,  H01L2924/0002

摘要： A self-aligned dielectric spacer is etched by providing capped gate structure along a second layer of dielectric material located above the gate cap material. Dopant material at an increased doping level is provided in the second layer of dielectric material where the self-aligned spacer is to be located. The second layer of dielectric material is then etched selective to the dopant to define the self-aligned dielectric spacer.

摘要翻译： 通过沿位于栅极帽材料上方的第二介电材料层提供封盖栅极结构来蚀刻自对准电介质间隔物。 增加掺杂浓度的掺杂剂材料被提供在第二绝缘材料层中，其中定位的自对准间隔物。 然后将第二层电介质材料选择性地蚀刻到掺杂剂以限定自对准电介质间隔物。

公开(公告)号：US20130268908A1

公开(公告)日：2013-10-10

申请号：US13443426

申请日：2012-04-10

申请人： Robert R. Arelt ,  Jeanne P. S. Bickford ,  Andrew D. Huber ,  Gustavo E. Tellez ,  Karl W. Vinson ,  Tina Wagner

发明人： Robert R. Arelt ,  Jeanne P. S. Bickford ,  Andrew D. Huber ,  Gustavo E. Tellez ,  Karl W. Vinson ,  Tina Wagner

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.

摘要翻译： 公开了将通孔有效地实现为多级集成电路布局的解决方案。 在各种实施例中，公开了一种创建具有至少一个通孔的多级集成电路布局的方法，所述方法包括：提供多层集成电路布局的至少两层; 以及选择用于连接所述至少两个层的通孔，其中所述选择包括从包括多个通孔类型的通孔库中检索所述通孔，所述多通道类型根据所述通孔库中的每一个的预测制造收益 多个通孔。

公开(公告)号：US20110166686A1

公开(公告)日：2011-07-07

申请号：US12652409

申请日：2010-01-05

申请人： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

发明人： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

IPC分类号： G06F17/50 ,  G06G7/66 ,  G06N5/02

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

摘要翻译： 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

公开(公告)号：US20090265673A1

公开(公告)日：2009-10-22

申请号：US12105299

申请日：2008-04-18

申请人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

发明人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

摘要翻译： 提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。 物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。 采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。 可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。

公开(公告)号：US20070037356A1

公开(公告)日：2007-02-15

申请号：US11585361

申请日：2006-10-23

申请人： Tina Wagner ,  Werner Rausch ,  Sadanand Deshpande

发明人： Tina Wagner ,  Werner Rausch ,  Sadanand Deshpande

IPC分类号： H01L21/8222

CPC分类号： H01L29/66772 ,  H01L29/78618

摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

摘要翻译： 提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。 栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。 通过将掺杂剂注入到其表面中，在栅电极的顶表面中形成薄的非晶硅覆盖层。 凹口蚀刻到盖层的周边。 在凹口中形成介电材料塞。 栅电极的侧壁被覆盖一部分插塞的侧壁间隔物覆盖，以消除栅极多晶硅的暴露，从而避免在形成升高的源极/漏极区域期间形成假外延生长。

公开(公告)号：US20070028195A1

公开(公告)日：2007-02-01

申请号：US11193711

申请日：2005-07-29

申请人： Dureseti Chidambarrao ,  Donald Jordan ,  Judith McCullen ,  David Onsongo ,  Tina Wagner ,  Richard Williams

发明人： Dureseti Chidambarrao ,  Donald Jordan ,  Judith McCullen ,  David Onsongo ,  Tina Wagner ,  Richard Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).

摘要翻译： 用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。 布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。