公开(公告)号：US08635575B2

公开(公告)日：2014-01-21

申请号：US13471627

申请日：2012-05-15

申请人： Henry A. Bonges, III

发明人： Henry A. Bonges, III

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072

摘要： Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.

摘要翻译： 通过连接与金属短路在同一网络上的相邻金属迹线来提高半导体芯片的产量和可靠性。 这减少和/或消除了以前在半导体芯片设计中使用的冗余通孔的需要。 另外，金属短裤被放置成符合一个或多个预定的设计规则。 一旦放置，检查金属短裤以确保每个金属短路连接基础清洁，从而确保放置是正确的。

公开(公告)号：US20090158230A1

公开(公告)日：2009-06-18

申请号：US11955653

申请日：2007-12-13

申请人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

发明人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

摘要翻译： 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

公开(公告)号：US07299426B2

公开(公告)日：2007-11-20

申请号：US10908803

申请日：2005-05-26

申请人： Henry A. Bonges, III

发明人： Henry A. Bonges, III

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072

摘要： Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.

摘要翻译： 通过连接与金属短路在同一网络上的相邻金属迹线来提高半导体芯片的产量和可靠性。 这减少和/或消除了以前在半导体芯片设计中使用的冗余通孔的需要。 另外，金属短裤被放置成符合一个或多个预定的设计规则。 一旦放置，检查金属短裤以确保每个金属短路连接基础清洁，从而确保放置是正确的。

公开(公告)号：US5313424A

公开(公告)日：1994-05-17

申请号：US852587

申请日：1992-03-17

申请人： Robert D. Adams ,  Henry A. Bonges, III ,  James W. Dawson ,  Erik L. Hedberg

发明人： Robert D. Adams ,  Henry A. Bonges, III ,  James W. Dawson ,  Erik L. Hedberg

IPC分类号： G11C29/00 ,  G11C29/12 ,  G11C29/44 ,  G11C13/00

CPC分类号： G11C29/72 ,  G11C29/44 ,  G11C29/78

摘要： A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.

摘要翻译： 提供一种形成在半导体芯片上的冗余系统，其包括用于测试存储器阵列以定位故障元件的电路，用于存储故障元件的地址的寄存器和响应于存储在该存储器中的地址的二进制数字而被熔断的电熔丝 在从单个输入施加到半导体芯片的使能信号时，进行寄存。 使能信号通过芯片上的逻辑电路，使得熔丝不能被编程或熔断，除非使能信号存在。 耦合到保险丝的输出的地址解码器代替用于故障元件的冗余元件。

公开(公告)号：US07132318B2

公开(公告)日：2006-11-07

申请号：US11003988

申请日：2004-12-04

申请人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

发明人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/0251

摘要： Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

摘要翻译： 公开了一种用于改变具有绝缘体上硅（SOI）晶体管的集成电路设计的方法和结构。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别可能在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 电网的跟踪），以及在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

公开(公告)号：US07120887B2

公开(公告)日：2006-10-10

申请号：US10707845

申请日：2004-01-16

申请人： Henry A. Bonges, III ,  Michael S. Gray ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker

发明人： Henry A. Bonges, III ,  Michael S. Gray ,  Jason D. Hibbeler ,  Kevin W. McCullen ,  Robert F. Walker

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.

摘要翻译： 用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。 本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。 联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

公开(公告)号：US5101120A

公开(公告)日：1992-03-31

申请号：US701392

申请日：1991-05-16

申请人： Henry A. Bonges, III ,  Roy C. Flaker

发明人： Henry A. Bonges, III ,  Roy C. Flaker

IPC分类号： H03K17/567 ,  G11C11/413 ,  H03K19/00 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K19/001

摘要： A BiCMOS output driver in which a bipolar device is driven by a control signal that biases the collector of an NFET. The control signal enables the bipolar to pull an output node to full potential (ground) quickly. The signal then falls within one nanosecond after the output reaches ground, pulling the bipolar out of saturation. A separate feedback device coupled between the base of the bipolar and ground can be added to pull the bipolar out of saturation before the control signal falls.

摘要翻译： BiCMOS输出驱动器，其中双极性器件由对NFET的集电极施加偏压的控制信号驱动。 控制信号使双极性能够快速地将输出节点拉到全电位（地）。 然后，信号在输出到达地面之后落在一纳秒内，将双极拉离饱和。 耦合在双极和地的基极之间的单独的反馈装置可以被添加以在控制信号下降之前将双极拉出饱和。

公开(公告)号：US20120227025A1

公开(公告)日：2012-09-06

申请号：US13471627

申请日：2012-05-15

申请人： Henry A. Bonges, III

发明人： Henry A. Bonges, III

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072

摘要： Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.

摘要翻译： 通过连接与金属短路在同一网络上的相邻金属迹线来提高半导体芯片的产量和可靠性。 这减少和/或消除了以前在半导体芯片设计中使用的冗余通孔的需要。 另外，金属短裤被放置成符合一个或多个预定的设计规则。 一旦放置，检查金属短裤以确保每个金属短路连接基础清洁，从而确保放置是正确的。

公开(公告)号：US08185859B2

公开(公告)日：2012-05-22

申请号：US11763781

申请日：2007-06-15

申请人： Henry A. Bonges, III

发明人： Henry A. Bonges, III

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5072

摘要： Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction.

摘要翻译： 通过连接与金属短路在同一网络上的相邻金属迹线来提高半导体芯片的产量和可靠性。 这减少和/或消除了以前在半导体芯片设计中使用的冗余通孔的需要。 另外，金属短裤被放置成符合一个或多个预定的设计规则。 一旦放置，检查金属短裤以确保每个金属短路连接基础清洁，从而确保放置是正确的。

公开(公告)号：US20090265673A1

公开(公告)日：2009-10-22

申请号：US12105299

申请日：2008-04-18

申请人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

发明人： Albrik Avanessian ,  Henry A. Bonges, III ,  Dureseti Chidambarrao ,  Stephen E. Greco ,  Douglas W. Kemerer ,  Tina Wagner

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.

摘要翻译： 提供了一种设计规则，其通过估计半导体芯片中的对应结构的物理重叠区域或“交叉区域”来确定两个相邻级别中的两个设计元素之间的重叠程度。 物理相交区域的估计可以考虑线边缘偏置，临界尺寸公差，覆盖公差和角舍入，以提供对应于两个设计元素的每个结构的物理面积的精确估计。 采用交叉区域作为度量以确定是否符合基本规则，即基于交叉区域来指定接地规则。 可以从交叉区域计算其他衍生量，例如电阻，电迁移阻力，预期产量，并且可以有利地用于优化设计数据。