公开(公告)号：US20070111447A1

公开(公告)日：2007-05-17

申请号：US11592020

申请日：2006-11-02

申请人： Carlo Cremonesi ,  Alessia Pavan ,  Giorgio Servalli

发明人： Carlo Cremonesi ,  Alessia Pavan ,  Giorgio Servalli

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, including the steps of: forming a gate dielectric over a surface of a semiconductor material layer; forming a conductive floating gate electrode insulated from the semiconductor material layer by the gate dielectric; forming at least one isolation region laterally to the floating gate electrode; excavating the at least one isolation region; filling the excavated isolation region with a conductive material; and forming a conductive control gate electrode of the floating gate MOS transistor insulatively over the floating gate, wherein the step of forming the floating gate electrode includes: laterally aligning the floating gate electrode to the at least one isolation region; and the step of excavating includes: lowering an isolation region exposed surface below a floating gate electrode exposed surface, the lowering exposing walls of the floating gate electrode; forming a protective layer on exposed walls of the floating gate electrode; and etching the at least one isolation region essentially down to the gate dielectric, the protective layer protecting against etching a portion of the at least one isolation region near the gate dielectric.

摘要翻译： 一种制造包括浮置栅极MOS晶体管的非易失性存储单元的方法，包括以下步骤：在半导体材料层的表面上形成栅极电介质; 通过栅极电介质形成与半导体材料层绝缘的导电浮栅电极; 与所述浮栅电极横向形成至少一个隔离区; 挖掘所述至少一个隔离区域; 用导电材料填充挖掘的隔离区域; 以及在所述浮置栅极上绝缘地形成所述浮置栅极MOS晶体管的导电控制栅电极，其中形成所述浮置栅电极的步骤包括：将所述浮置栅极横向对准所述至少一个隔离区; 并且所述挖掘步骤包括：降低浮栅电极暴露表面下方的隔离区域暴露表面，所述浮栅电极的下降暴露壁; 在浮栅电极的暴露壁上形成保护层; 以及基本上将所述至少一个隔离区域蚀刻到所述栅极电介质，所述保护层防止蚀刻所述栅极电介质附近的所述至少一个隔离区域的一部分。

公开(公告)号：US07125807B2

公开(公告)日：2006-10-24

申请号：US10746878

申请日：2003-12-23

申请人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

发明人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC分类号： H01L21/302 ,  H01B13/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

摘要翻译： 半导体衬底具有由绝缘层的部分限定的有源区域。 在衬底上形成隧道氧化物薄层，然后沉积第一层导电材料。 通过限定浮动栅极区域在其上制造非易失性存储器单元。 这些浮动栅极区域的定义涉及限定第一层导电材料，以便形成由有缺陷条纹的有源区域交替的一对有源区域之上的多个交替条纹。 然后在交替条纹的侧壁的遮蔽物中形成间隔物。 然后第二层导电材料与第一层导电材料一起沉积。 然后选择性地去除间隔物。

公开(公告)号：US07326615B2

公开(公告)日：2008-02-05

申请号：US11319750

申请日：2005-12-27

申请人： Alessia Pavan ,  Giorgio Servalli ,  Cesare Clementi

发明人： Alessia Pavan ,  Giorgio Servalli ,  Cesare Clementi

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

摘要翻译： 一种方法在包括存储器单元矩阵和相关电路的半导体衬底上制造非易失性存储器件。 该方法包括：在整个衬底上形成填充电介质层，直到电池的栅极和电路的导电层被完全覆盖，去除电介质层，直到电池的栅极和导电层的上部被暴露，限定 导电层中的电路的晶体管的多个栅电极，以及形成衬底中的电路的晶体管的源区和漏极区。 该方法还包括：在电路的晶体管的栅电极的侧壁上形成间隔物，并且在电路的电极上的栅电极上形成硅单元的电极上的硅化物层，并在电源的源极和漏极区 所述电路的晶体管。

公开(公告)号：US20060166439A1

公开(公告)日：2006-07-27

申请号：US11319750

申请日：2005-12-27

申请人： Alessia Pavan ,  Giorgio Servalli ,  Cesare Clementi

发明人： Alessia Pavan ,  Giorgio Servalli ,  Cesare Clementi

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

摘要： A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

摘要翻译： 一种方法在包括存储器单元矩阵和相关电路的半导体衬底上制造非易失性存储器件。 该方法包括：在整个衬底上形成填充电介质层，直到电池的栅极和电路的导电层被完全覆盖，去除电介质层，直到电池的栅极和导电层的上部被暴露，限定 导电层中的电路的晶体管的多个栅电极，以及形成衬底中的电路的晶体管的源区和漏极区。 该方法还包括：在电路的晶体管的栅电极的侧壁上形成间隔物，并且在电路的电极上的栅电极上形成硅单元的电极上的硅化物层，并在电源的源极和漏极区 所述电路的晶体管。

公开(公告)号：US20080211009A1

公开(公告)日：2008-09-04

申请号：US12070175

申请日：2008-02-14

申请人： Giorgio Servalli ,  Daniela Brazzelli ,  Sonia Costantini ,  Alessia Pavan

发明人： Giorgio Servalli ,  Daniela Brazzelli ,  Sonia Costantini ,  Alessia Pavan

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11546

摘要： An embodiment of a process is described for manufacturing a non volatile memory electronic device integrated on a semiconductor substrate which comprises a matrix of non volatile memory cells, the memory cells being organized in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors and low voltage transistors, the process comprising the steps for realizing: gate electrodes of the non volatile memory cells which comprise at least one first conductive layer, one first insulating layer, one second conductive layer and one third conductive layer and are insulated from the semiconductor substrate by means of a second insulating layer, gate electrodes of high voltage transistors which comprise the at least one first conductive layer whereon the third polysilicon layer is overlapped and is insulated from the semiconductor substrate by means of a third insulating layer of greater thickness than the second insulating layer, gate electrodes of low voltage transistors which comprise the second conductive layer whereon the third conductive layer is overlapped and are insulated from the semiconductor substrate by means of a fourth insulating layer.

摘要翻译： 描述了用于制造集成在半导体衬底上的非易失性存储器电子器件的实施例，该非易失性存储器电子器件包括非易失性存储器单元矩阵，存储器单元被组织成行，称为字线，以及称为位线的列和 包括高压晶体管和低压晶体管的相关电路，该方法包括以下步骤：非易失性存储单元的栅电极，其包括至少一个第一导电层，一个第一绝缘层，一个第二导电层和一个第三导电层 并且通过第二绝缘层与半导体衬底绝缘，高压晶体管的栅电极包括第三多晶硅层重叠的至少一个第一导电层，并且通过第三绝缘体与半导体衬底绝缘 层厚度大于第二绝缘层，栅极e 包含第三导电层的第二导电层的低电压晶体管的导电极叠层，并通过第四绝缘层与半导体衬底绝缘。

公开(公告)号：US07125808B2

公开(公告)日：2006-10-24

申请号：US10749020

申请日：2003-12-29

申请人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

发明人： Cesare Clementi ,  Alessia Pavan ,  Livio Baldi

IPC分类号： H01L21/302 ,  H01B13/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

摘要翻译： 描述了一种用于在具有由绝缘层的部分界定的有源区域的半导体衬底上制造非易失性存储器单元的方法。 形成隧道氧化物的薄层，然后沉积第一层导电材料。 通过仅在交替的有效区域对之上形成屏蔽材料条来限定多个浮动栅极区域。 选择性材料的间隔相对于屏蔽材料限定，并且在如此限定的条纹的侧壁的遮蔽物中随意地被限定。 屏蔽材料也沉积在缺乏它的有源区上。 通过将浮动栅极区域之间的距离定义为间隔物来完成浮栅的形成。