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公开(公告)号：US07257791B2
公开(公告)日：2007-08-14
申请号：US10992999
申请日：2004-11-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.
摘要翻译： 使用基于缓冲器高度，输入电容，输出电容和延迟时间来识别缓冲器类型的表，将缓冲器插入到集成电路芯片设计中。 创建具有根，内部和叶子顶点的缓冲区路由树。 对于每个内部顶点，将初始电路参数与与表中标识的缓冲器相关联的电路参数进行比较，以识别表中识别的缓冲区是否可以插入到相应的内部顶点。 如果可以，则至少部分地基于比较结果，从表中选择最佳可插入缓冲器并将其插入到选定的内部顶点。 还描述了创建缓冲器类型表的计算机处理。
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公开(公告)号：US07246336B2
公开(公告)日：2007-07-17
申请号：US11004309
申请日：2004-12-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
摘要翻译： 描述了一种用于计算具有在一个或多个闭合回路中的定向图中互连的引脚的集成电路布图图案的突发时间传播的方法。 对于第一组引脚计算Ramptime值，它们不连接到闭环，同时留下第二组引脚具有未知的ramptime值。 一个或多个闭环通过从第二组中的引脚回溯具有未知的ramptime值来识别。 迭代地计算一个或多个闭环中每个引脚的ramptime值。
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公开(公告)号：US07146591B2
公开(公告)日：2006-12-05
申请号：US10992941
申请日：2004-11-19
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.
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4.发明授权Method and apparatus for performing logical transformations for global routing 失效用于执行全局路由的逻辑转换的方法和装置公开(公告)号：US07398486B2
公开(公告)日：2008-07-08
申请号：US10803516
申请日：2004-03-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077
摘要： The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters. This may be achieved by assigning the same coordinates to nodes of degree !=2 of homeomorphic trees, which means that one may assign the coordinates of corresponding nodes to “essential” nodes and then insert or remove nodes of degree 2.
摘要翻译： 本发明提供了一种用于优化全局路由中的各种设计参数的新方法和算法。 根据本发明的示例性方面，首先对标记的树进行预处理。 对于每个离开的顶点，可以通过它的叶子列表，如果两个叶子有相同的标记，那么可以只留下其中一个。 之后，可以确定是否存在同胚。 选择这种同胚对之后的原因如下：添加或删除2级顶点以及添加或删除新叶（变量）不会显着修改路由（在这种情况下，所有路由转换本质上都是分割和合并路由 树）。 选择适用的变换后，可以应用它们来优化设计参数。 这可以通过将相同的坐标分配给同胚树的度数= 2的节点来实现，这意味着可以将对应节点的坐标分配给“必需”节点，然后插入或移除度数2的节点。
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公开(公告)号：US07496870B2
公开(公告)日：2009-02-24
申请号：US11551573
申请日：2006-10-20
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.
摘要翻译： 本公开涉及一种用于选择用于原始设计的逻辑重组的集成电路中的单元的方法。 原始设计包括一组参数。 该方法包括形成将包括用于逻辑重组的所选择的单元的重构集合和候选集。 重组集合包括具有初始单元格的重组单元。 重组集合适于接受被称为重组细胞的额外细胞。 候选集合适于包括候选小区，其中候选集合中的每个候选小区连接到重组集合中的至少一个重组小区。 候选集合适于从候选集中移除候选细胞。 如果在参数集合中包括相应的参数，则重组集合适于接受所选择的被移除的候选小区作为已识别的重组小区。
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公开(公告)号：US07568175B2
公开(公告)日：2009-07-28
申请号：US11757229
申请日：2007-06-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
摘要翻译： 描述了一种用于计算具有在一个或多个闭环中的定向图中互连的引脚的集成电路布图图案的突触传播的方法和装置。 对于第一组引脚计算Ramptime值，它们不连接到闭环，同时留下第二组引脚具有未知的ramptime值。 一个或多个闭环通过从第二组中的引脚回溯具有未知的ramptime值来识别。 迭代地计算一个或多个闭环中每个引脚的ramptime值。
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7.发明授权Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths 有权在没有增加线长度的情况下将坐标分配给逻辑树的节点的过程和设备公开(公告)号：US07111267B2
公开(公告)日：2006-09-19
申请号：US10928799
申请日：2004-08-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.
摘要翻译： 迭代过程将新逻辑树的节点分配给先前分配给等同于新逻辑树的旧逻辑树的空间中的位置。 新树中的路径被标识为新树的基本节点。 为相当于基本节点的子节点的旧树节点识别空间位置的坐标。 使用自由空间算法并且基于新树路径的节点和为相同于基本节点的儿子的旧树节点识别的坐标，迭代地识别新树路径中的每个节点的坐标。 如果基本节点的所有儿子都是新树的叶子，那么旧的树节点就是与子节点相当的叶节点。 否则，在先前的迭代中识别旧树节点。
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公开(公告)号：US06637016B1
公开(公告)日：2003-10-21
申请号：US09841824
申请日：2001-04-25
申请人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
发明人： Elyar E. Gasanov , Andrej A. Zolotykh , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A method for selectively placing cells of an application-specific integrated circuit on a substrate surface, including the steps of defining a grid covering a substrate surface, assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid, grouping the cells by function to provide functional regions within the grid, determining a density map of the surface of the substrate in all the functional regions within the grid, determining free space of the grid on the surface of the substrate relative to the density map, and assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit. Use of the method provides improved layout of an integrated circuit with minimal cell congestion or overlapping.
摘要翻译： 一种用于选择性地将专用集成电路的单元放置在衬底表面上的方法，包括以下步骤：限定覆盖衬底表面的栅格，将单元分配给栅格以提供单元相对于栅格的旧x和y坐标， 通过功能对细胞进行分组以在网格内提供功能区域，确定网格内所有功能区域中基底表面的密度图，确定基底表面上的网格相对于密度图的自由空间， 并将新的单元分配给衬底表面上的栅格的自由空间以提供专用集成电路。 该方法的使用提供了具有最小的信元拥塞或重叠的集成电路的改进布局。
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9.发明授权Method and apparatus for local resynthesis of logic trees with multiple cost functions 有权具有多个成本函数的逻辑树的局部再合成方法和装置公开(公告)号：US06543032B1
公开(公告)日：2003-04-01
申请号：US09678479
申请日：2000-10-02
IPC分类号： G06F1715
CPC分类号： G06F17/505
摘要： Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.
摘要翻译： 提供了用于优化集成电路设计的系统和技术，其中在集成电路设计中识别关键区域，并且在临界区域中应用多个备选标识，以获得相应的多个结果。 然后，替代表示被识别为多个结果中的代表性表示，根据该结果，突发时间和定时中的至少一个被改进，并且基于指定的优先级来选择替代表示中的最佳替代表示来替换到临界区，所述优先级包括：（i ）选择基于减少违约时间; （ii）从基于时间改进保留细胞区域的替代表示中进行选择; 和（iii）如果所有替代表示增加单元格区域，则基于对时间递减和面积增量之间的关系的评估进行选择。
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公开(公告)号：US06701503B2
公开(公告)日：2004-03-02
申请号：US10072008
申请日：2002-02-07
IPC分类号： G06F945
CPC分类号： G06F17/5072
摘要： The present invention is directed to a system and method for providing an overlap remover manager. A method for removing overlaps in a circuit design for an integrated circuit may include initiating an overlap remover manager, wherein the overlap remover manager is suitable for moving cells of an integrated circuit design to remove cell overlaps. A search for critical wires is performed and a determination is made of which violated moves of cells caused at least one critical wire. A determined violated move of the cells is rolled back and the overlap remover manager employed to remove overlaps between rolled back cells.
摘要翻译： 本发明涉及一种用于提供重叠去除器管理器的系统和方法。 用于去除集成电路的电路设计中的重叠的方法可以包括启动重叠去除器管理器，其中重叠去除器管理器适合于移动集成电路设计的单元以去除单元重叠。 执行关键线的搜索，并且确定哪些违反移动的单元造成至少一个关键线。 回滚确定的单元格的违反移动，并且使用重叠去除器管理器来去除回滚单元之间的重叠。
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