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    Test structures and method for interconnect impedance property extraction
    5.
    发明授权
    Test structures and method for interconnect impedance property extraction 有权
    互连阻抗特性提取的测试结构和方法

    公开(公告)号：US07340703B2

    公开(公告)日：2008-03-04

    申请号：US10975717

    申请日：2004-10-26

    申请人： Hazem Mahmoud Hegazy ,  Amr M. E. Safwat ,  Wael Fikry Farouk Fikry Abdalla

    发明人： Hazem Mahmoud Hegazy ,  Amr M. E. Safwat ,  Wael Fikry Farouk Fikry Abdalla

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2853 ,  G01R27/28 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and test structures are disclosed for characterizing interconnects of an integrated circuit. The method provides a set of test structures and determines a unit impedance property of each test structure, desirably using S-parameter measurements. A reference impedance data set is then formulated that characterizes the impedance of an integrated circuit manufacturing technology and that can be used to characterize the impedance of interconnects of the chip made by the technology. Each test structure desirably comprises a ground grid and a signal line, and is characterized by values of a set of predetermined attributes such as layer location of the respective ground grid, grid density, layer association, width and length of the respective signal line.

    摘要翻译： 公开了用于表征集成电路的互连的方法和测试结构。 该方法提供一组测试结构，并确定每个测试结构的单位阻抗特性，最好使用S参数测量。 然后制定参考阻抗数据集，其表征集成电路制造技术的阻抗，并且可以用于表征由该技术制造的芯片的互连的阻抗。 每个测试结构理想地包括接地网格和信号线，并且其特征在于一组预定属性的值，例如各个接地网格的层位置，网格密度，层关联，各个信号线的宽度和长度。