公开(公告)号：US20110306721A1

公开(公告)日：2011-12-15

申请号：US13134100

申请日：2011-05-27

Applicant: Veerag Mehta ,  David Romenesko ,  Anand Mishra

Inventor： Veerag Mehta ,  David Romenesko ,  Anand Mishra

IPC: C08L83/00 ,  C09K21/14

CPC classification number: C08K5/0066 ,  C08G77/12 ,  C08G77/16 ,  C08G77/20 ,  C08K3/016 ,  C08L83/04

Abstract: A process for preparing fire retardant materials having enhanced lubricity, wherein the process comprises providing a silicone, curable, fire retardant material and partially curing the curable fire retardant material to a semi-fluid, gum-like gel prior to any end use application.

Abstract translation: 一种用于制备具有增强的润滑性的阻燃材料的方法，其中所述方法包括在任何最终使用应用之前提供硅树脂，可固化的阻燃材料，并将可固化的阻燃材料部分固化成半流体，胶状凝胶。

公开(公告)号：US08526246B2

公开(公告)日：2013-09-03

申请号：US13370035

申请日：2012-02-09

Applicant: Siddharth Gupta ,  Nitin Jain ,  Anand Mishra

Inventor： Siddharth Gupta ,  Nitin Jain ,  Anand Mishra

IPC: G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。

公开(公告)号：US20120140582A1

公开(公告)日：2012-06-07

申请号：US13370035

申请日：2012-02-09

Applicant: Siddharth GUPTA ,  Nitin Jain ,  Anand Mishra

Inventor： Siddharth GUPTA ,  Nitin Jain ,  Anand Mishra

IPC: G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。

公开(公告)号：US08130567B2

公开(公告)日：2012-03-06

申请号：US12641102

申请日：2009-12-17

Applicant: Siddharth Gupta ,  Nitin Jain ,  Anand Mishra

Inventor： Siddharth Gupta ,  Nitin Jain ,  Anand Mishra

IPC: G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。

公开(公告)号：US20100157699A1

公开(公告)日：2010-06-24

申请号：US12641102

申请日：2009-12-17

Applicant: Siddharth GUPTA ,  Nitin JAIN ,  Anand MISHRA

Inventor： Siddharth GUPTA ,  Nitin JAIN ,  Anand MISHRA

IPC: G11C11/416 ,  G11C8/00 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。