公开(公告)号：US20070067706A1

公开(公告)日：2007-03-22

申请号：US10557375

申请日：2004-05-14

申请人： Mohamed Azimane ,  Ananta Majhi

发明人： Mohamed Azimane ,  Ananta Majhi

IPC分类号： H04L1/00

CPC分类号： G11C29/02

摘要： Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types of faults is proposed, in which two cells of two logically adjacent rows or columns are written with complementary logic data. If a read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect is demonstrated. The read and write operations each occur as a result of a clock pulse, and the method includes the steps of setting a clock cycle such that, in the event that said first cell is demonstrating slow-to-fall behavior, the reading cycle will be caused to be performed before the logic state of said first cell has fallen to its minimum level, and/or of setting the width of said clock pulses such that, in the event that the first cell is demonstrating slow-to-rise behavior, the reading cycle will be caused to be performed before the logic state of said first cell has risen to its maximum level.

摘要翻译： 例如地址解码器和导致逻辑和顺序延迟行为的电压源的逻辑门之间的硬开放缺陷使得存储器在条件上不起作用。 提出了一种用于测试这些类型故障的集成电路的方法和装置，其中两个逻辑相邻的行或列的两个单元被写入互补逻辑数据。 如果读取操作显示两个单元格中的数据相同，则会显示硬开放缺陷的存在和位置。 读取和写入操作各自作为时钟脉冲的结果而发生，并且该方法包括设置时钟周期的步骤，使得在所述第一小区示出缓慢到下降的行为的情况下，读取周期将是 导致在所述第一单元的逻辑状态已经下降到其最小电平之前执行，和/或设置所述时钟脉冲的宽度，使得在第一单元显示缓慢上升行为的情况下， 在所述第一单元的逻辑状态上升到其最大电平之前，将执行读取周期。

公开(公告)号：US20070257716A1

公开(公告)日：2007-11-08

申请号：US10591193

申请日：2005-03-03

申请人： Mohamed Azimane ,  Ananta Majhi

发明人： Mohamed Azimane ,  Ananta Majhi

IPC分类号： H03L7/00

CPC分类号： G11C29/48 ,  G11C29/024 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56012

摘要： The present invention relates to a test system (100) interposed between a clock monitor self-timed memory. In an example embodiment, the test system (100) receives an internal clock signal (104) from the clock monitor (152), an external clock signal (CL) and a control signal (CS). A multiplexer (110) of the test system provides in dependence upon the control signal (CS) the internal clock signal (104) to the internal memory block (125) during a normal mode of operation of the self-timed memory and the external clock signal (CL) to the internal memory block (125) during a test mode (108) of the self-timed memory. The test system (100) enables control of the clock cycle of the internal memory block (125) by directly applying the external clock signal (CL) during test mode. Thus, the internal memory block is stressed properly enabling the detection of small delay faults.

摘要翻译： 本发明涉及一种插在时钟监视器自定时存储器之间的测试系统（100）。 在示例性实施例中，测试系统（100）从时钟监视器（152），外部时钟信号（CL）和控制信号（CS）接收内部时钟信号（104）。 在自定时存储器和外部时钟的正常操作模式期间，测试系统的多路复用器（110）根据控制信号（CS）提供内部存储器块（125）的内部时钟信号（104） 在自定时存储器的测试模式（108）期间向内部存储器块（125）发送信号（CL）。 测试系统（100）通过在测试模式期间直接施加外部时钟信号（CL）来实现内部存储器块（125）的时钟周期的控制。 因此，内部存储器块被适当地压缩，能够检测到小的延迟故障。