公开(公告)号：US5884060A

公开(公告)日：1999-03-16

申请号：US820715

申请日：1997-03-18

申请人： Anantakotiraju Vegesna ,  Jayachandra B. Avula ,  Peter H. Jewett ,  Yatin G. Mundkur ,  Vinay J. Naik ,  James E. Monaco

发明人： Anantakotiraju Vegesna ,  Jayachandra B. Avula ,  Peter H. Jewett ,  Yatin G. Mundkur ,  Vinay J. Naik ,  James E. Monaco

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/30112 ,  G06F9/30127 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： An apparatus and method for scheduling the execution of one or more of a sequence of instructions for superscalar execution by a central processing unit during a single clock cycle of the processor clock is disclosed wherein the scheduling process is performed in a manner which does not dictate the duration of the processor clock period. During the decode stage of the processor pipeline, the instructions are classified, decoded, and data and resource dependencies are detected and resolved for operand access, with these processes being performed virtually in parallel so that the instructions can be appropriately scheduled for execution at the beginning of the next processor clock cycle. Because of the parallel nature of the scheduling process, scheduling can be performed and completed fast enough that processes other than instruction scheduling will dictate the minimum processor clock period.

摘要翻译： 公开了一种用于在处理器时钟的单个时钟周期期间调度由中央处理单元进行超标量执行的一系列指令的执行的装置和方法，其中调度过程以不规定 处理器时钟周期的持续时间。 在处理器流水线的解码阶段，指令被分类，解码，数据和资源相关性被检测和解决用于操作数访问，这些进程实际上是并行执行的，使得指令可以被适当地安排在开始执行 的下一个处理器时钟周期。 由于调度过程的并行性质，可以快速执行调度并完成调度，除了指令调度之外的处理将决定最小处理器时钟周期。

公开(公告)号：US5226142A

公开(公告)日：1993-07-06

申请号：US615704

申请日：1990-11-21

申请人： Anantakotiraju Vegesna ,  Steve Studulski ,  Peter Jewett ,  Sang Yoo

发明人： Anantakotiraju Vegesna ,  Steve Studulski ,  Peter Jewett ,  Sang Yoo

IPC分类号： G06F9/30 ,  G06F9/46 ,  G11C8/16

CPC分类号： G06F9/30127 ,  G06F9/30098 ,  G06F9/462 ,  G11C8/16

摘要： A register file within a central processing unit which processes operations on operands stored in the register file is disclosed. The register file includes a plurality of memory locations and each of the memory locations provides the physical storage for one or more registers. Each memory location stores one of the operands. The register file also includes a plurality of windows and each of the windows provides a unique mapping of the same set of registers to an equal number of memory location and each window includes the same quantity of one or more registers. A pointer points to one of the windows of the register file for indicating which window is currently active. Each of the memory locations is coupled to at least one multiplexer. The active memory locations of the active window, currently assigned to provide storage for the registers, simultaneously output to the at least one multiplexer the operands stored in the registers. Each of the at least one multiplexers obtains one of the operands of the active window and outputs the operand to the central processing unit for processing.

摘要翻译： 公开了处理对存储在寄存器文件中的操作数的操作的中央处理单元内的寄存器文件。 寄存器文件包括多个存储器位置，并且每个存储器位置为一个或多个寄存器提供物理存储。 每个存储器位置存储一个操作数。 寄存器文件还包括多个窗口，并且每个窗口提供相同寄存器组的唯一映射到相等数量的存储器位置，并且每个窗口包括相同量的一个或多个寄存器。 指针指向寄存器文件的一个窗口，用于指示当前处于活动状态的窗口。 每个存储器位置耦合到至少一个多路复用器。 当前分配给提供存储器的寄存器的活动窗口的活动存储器位置同时向至少一个多路复用器输出存储在寄存器中的操作数。 至少一个多路复用器中的每一个获得活动窗口的一个操作数，并将该操作数输出到中央处理单元进行处理。

公开(公告)号：US5640588A

公开(公告)日：1997-06-17

申请号：US592989

申请日：1996-01-29

申请人： Anantakotiraju Vegesna ,  Jayachandra B. Avula ,  Peter H. Jewett ,  Yatin G. Mundkur ,  Vinay J. Naik ,  James E. Monaco

发明人： Anantakotiraju Vegesna ,  Jayachandra B. Avula ,  Peter H. Jewett ,  Yatin G. Mundkur ,  Vinay J. Naik ,  James E. Monaco

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30112 ,  G06F9/30127 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.

摘要翻译： 一种用于调度用于实现中央处理单元内的指令的多次启动和多次执行的指令序列的装置和方法。 根据中央处理单元的多个执行资源中的哪一个执行指令来分类每个指令。 分类包括内存引用操作，整数运算，程序控制操作和浮点运算。 与指令相关联的分类按顺序发生的顺序发生。

公开(公告)号：US5488729A

公开(公告)日：1996-01-30

申请号：US208091

申请日：1994-03-07

申请人： Anantakotiraju Vegesna ,  Jayachandra B. Avula ,  Peter H. Jewett ,  Yatin G. Mundkur

发明人： Anantakotiraju Vegesna ,  Jayachandra B. Avula ,  Peter H. Jewett ,  Yatin G. Mundkur

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/16 ,  G06F9/28

CPC分类号： G06F9/30112 ,  G06F9/30127 ,  G06F9/3013 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execution resources of the central processing unit executes the instruction. The classifications include memory reference operations, integer operations, program control operations, and floating point arithmetic operations. The classifications associated with the instructions occur in the order in which the instructions occur in the sequence.

摘要翻译： 一种用于调度用于实现中央处理单元内的指令的多次启动和多次执行的指令序列的装置和方法。 根据中央处理单元的多个执行资源中的哪一个执行指令来分类每个指令。 分类包括内存引用操作，整数运算，程序控制操作和浮点运算。 与指令相关联的分类按顺序发生的顺序发生。