公开(公告)号：US06629208B2

公开(公告)日：2003-09-30

申请号：US09924289

申请日：2001-08-08

申请人： Andrew Craig Sturges ,  David May

发明人： Andrew Craig Sturges ,  David May

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0888

摘要： A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

公开(公告)号：US06594729B1

公开(公告)日：2003-07-15

申请号：US09155607

申请日：1999-05-17

申请人： Andrew Craig Sturges ,  David May

发明人： Andrew Craig Sturges ,  David May

IPC分类号： G06F1208

CPC分类号： G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

摘要： A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

公开(公告)号：US06460105B1

公开(公告)日：2002-10-01

申请号：US09302685

申请日：1999-04-29

申请人： Andrew Michael Jones ,  Andrew Keith Betts ,  Glenn Ashley Farrall ,  Brian Foster ,  Andrew Craig Sturges

发明人： Andrew Michael Jones ,  Andrew Keith Betts ,  Glenn Ashley Farrall ,  Brian Foster ,  Andrew Craig Sturges

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.

摘要翻译： 描述了中断的传输，其中中断在外围设备处由导体的电平表示，但是通过沿着路由路径路由的消息分组被传送到接收模块。 根据一方面，消息分组包括产生中断的外围设备的标识，并且接收模块根据外围设备的标识来执行消息分组以实现中断处理例程。 根据另一方面，消息分组包括唯一地标识一系列中断之一的事务标识符，并且接收模块生成包含该事务标识符的响应分组，从而允许外围设备监视其中断是否已被正确处理 。

公开(公告)号：US06295580B1

公开(公告)日：2001-09-25

申请号：US09014194

申请日：1998-01-27

申请人： Andrew Craig Sturges ,  David May

发明人： Andrew Craig Sturges ,  David May

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0888

摘要： A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

摘要翻译： 在其中处理器能够执行多个处理的系统中描述了操作高速缓冲存储器的方法，每个处理包括一系列指令。 在该方法中，高速缓冲存储器被分为高速缓存分区，每个高速缓存分区具有多个可寻址存储位置，用于保存高速缓冲存储器中的项目。 分配指示符被分配给每个进程，标识哪个（如果有的话）所述高速缓存分区将用于保存用于执行该进程的项目。 当处理器在执行所述当前进程期间请求来自主存储器的项目并且该项目不被保存在高速缓冲存储器中时，该项目从主存储器中取出并被加载到所识别的高速缓存分区中的多个可寻址存储位置之一中。

公开(公告)号：US06871266B2

公开(公告)日：2005-03-22

申请号：US10446280

申请日：2003-05-23

申请人： Andrew Craig Sturges ,  David May

发明人： Andrew Craig Sturges ,  David May

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

摘要： A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

公开(公告)号：US06453385B1

公开(公告)日：2002-09-17

申请号：US09014315

申请日：1998-01-27

申请人： Andrew Craig Sturges ,  David May ,  Glenn Farrall ,  Bruno Fel ,  Catherine Barnaby

发明人： Andrew Craig Sturges ,  David May ,  Glenn Farrall ,  Bruno Fel ,  Catherine Barnaby

IPC分类号： G06F1200

CPC分类号： G06F12/126 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0888

摘要： A cache system and method of operating are described in which a cache is connected between a processor and a main memory of a computer. The cache system includes a cache memory having a set of cache partitions. Each cache partition has a plurality of addressable storage locations for holding items fetched from said main memory for use by the processor. The cache system also includes a cache refill mechanism arranged to fetch an item from the main memory and to load said item into the cache memory at one of said addressable storage locations in a cache partion wich depends on the address of said item in the main memory. This is achieved by a cache partition access table holding in association with addresses of items to be cached respective multi-bit partition indications identifying one or more cache partition into which the item is to be loaded.

摘要翻译： 描述了缓存系统和操作方法，其中高速缓存连接在计算机的处理器和主存储器之间。 缓存系统包括具有一组高速缓存分区的高速缓冲存储器。 每个高速缓存分区具有多个可寻址的存储位置，用于保存从所述主存储器取出以供处理器使用的项目。 高速缓存系统还包括高速缓冲存储器补充机构，其被配置为从主存储器中取出一个物品，并且在高速缓存部分中的所述可寻址存储位置中的一个位置将所述物品加载到高速缓存存储器中，该高速缓存部分依赖于主存储器中的所述项目的地址 。 这通过与要缓存的项目的地址相关联的高速缓存分区访问表来实现，该缓存分区访问表标识识别要加载项目的一个或多个高速缓存分区的相应的多位分区指示。

公开(公告)号：US6009508A

公开(公告)日：1999-12-28

申请号：US938242

申请日：1997-09-26

申请人： Michael David May ,  Andrew Craig Sturges ,  Nathan Mackenzie Sidwell

发明人： Michael David May ,  Andrew Craig Sturges ,  Nathan Mackenzie Sidwell

IPC分类号： G06F9/30 ,  G06F13/00

CPC分类号： G06F9/30167 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30178 ,  G06F9/3816

摘要： A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis. This therefore increases the number of data values that can be held in relation to the number of addresses that can be identified by the second set of bit locations.A method of executing a succession of instructions in a computer system is also described.

摘要翻译： 计算机系统具有相对于在指令执行期间可能保持的数据项的数量减少地址位数的指令。 指令集包括可选择的指令，多个指令各自包括标识要通过执行指令执行的操作的一组比特位置和第二组比特位置，以识别数据存储位置的地址，以用于 执行指令。 计算机系统还包括多个可寻址数据存储位置，用于在执行指令序列期间同时保持多个数据值，其中至少一个数据存储位置包括要求指令中的单个地址的多值存储 并且被安排成以先入先出的方式同时保存多个数据值。 因此，这增加了可以相对于可由第二组位位置识别的地址数量来保持的数据值的数量。 还描述了在计算机系统中执行一系列指令的方法。

公开(公告)号：US06564314B1

公开(公告)日：2003-05-13

申请号：US08472515

申请日：1995-06-07

申请人： Michael David May ,  Andrew Craig Sturges ,  Nathan Mackenzie Sidwell

发明人： Michael David May ,  Andrew Craig Sturges ,  Nathan Mackenzie Sidwell

IPC分类号： G06F1500

CPC分类号： G06F9/30178 ,  G06F9/30156 ,  G06F9/30163 ,  G06F9/3816

摘要： A computer system has compact instructions avoiding the need for redundant bit locations and needing simple decoding. Logic circuitry is arranged to respond to an instruction set comprising a plurality of selectable instructions of different bit lengths. Each instruction is based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length. Some instructions omit a selected one of the fields and include an identifier of less bit length than the omitted field to indicate which field is omitted. Thus this bit length of the instruction is compressed. The logic circuitry is operable to restore the omitted field on execution of the instruction.

摘要翻译： 计算机系统具有紧凑的指令，避免需要冗余位位置并且需要简单的解码。 逻辑电路被布置为响应包括不同位长度的多个可选择指令的指令集。 每个指令基于预定比特长度的格式和各个预定比特长度的预定指令字段序列。 一些指令省略了所选择的一个字段，并且包括比省略的字段少的位长度的标识符，以指示哪个字段被省略。 因此，指令的该位长度被压缩。 逻辑电路可操作以在执行指令时恢复省略的字段。