公开(公告)号：US20070022204A1

公开(公告)日：2007-01-25

申请号：US11186183

申请日：2005-07-21

申请人： Andrew Moch ,  Aaron Rossetto ,  Brent Schwan ,  Glen Sescila

发明人： Andrew Moch ,  Aaron Rossetto ,  Brent Schwan ,  Glen Sescila

IPC分类号： G06F15/16

CPC分类号： H04L1/24 ,  H04L43/50 ,  H04L2001/0094

摘要： A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.

摘要翻译： 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。

公开(公告)号：US20050080954A1

公开(公告)日：2005-04-14

申请号：US10936088

申请日：2004-09-08

申请人： Rafael Castro ,  Andrew Moch ,  Sean Nickel

发明人： Rafael Castro ,  Andrew Moch ,  Sean Nickel

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4059

摘要： A system and method for buffering bidirectional digital I/O lines. The system (e.g., data acquisition system) may comprise a device including circuitry for buffering bidirectional digital lines. A first IC of the device preferably includes a first and a second bidirectional buffer coupled to a first bidirectional digital I/O line, and a second IC of the device preferably includes a third bidirectional buffer. The first IC and the second IC may also each include a control unit to control a driving direction of the corresponding bidirectional buffers independently to change the direction of a data flow through the first bidirectional digital I/O line from a first direction to a second direction. The driving direction of the bidirectional buffers may be changed at different times in a particular sequence, and the order may depend on whether the direction change is from the output direction to the input direction or vice versa.

摘要翻译： 一种用于缓冲双向数字I / O线的系统和方法。 系统（例如，数据采集系统）可以包括包括用于缓冲双向数字线路的电路的设备。 该装置的第一IC优选地包括耦合到第一双向数字I / O线的第一和第二双向缓冲器，并且该装置的第二IC优选地包括第三双向缓冲器。 第一IC和第二IC还可以各自包括控制单元，用于独立地控制相应的双向缓冲器的驱动方向，以便通过第一双向数字I / O线从第一方向到第二方向改变数据流的方向 。 双向缓冲器的驱动方向可以在特定顺序的不同时间改变，并且顺序可以取决于方向改变是从输出方向到输入方向，反之亦然。

公开(公告)号：US06594612B2

公开(公告)日：2003-07-15

申请号：US09735234

申请日：2000-12-11

申请人： Andrew Moch

发明人： Andrew Moch

IPC分类号： G06F1900

CPC分类号： G06F11/24

摘要： A digitizer for use in a measurement system. The digitizer acquires data from an external source, and includes a static random access memory (SRAM) which stores a scan list comprising entries specifying digitizer operations such as switch time, settle time, measure time, looping, and mathematical operation specifications such as scaling, adding, and averaging specifications. The looping specification may include instructions to repeatedly execute one or more entries in the scan list. The digitizer includes a programmable logic element (e.g. an FPGA) coupled to the SRAM which accesses and executes the scan list to acquire analog signals from the source. The digitizer may include an analog-to-digital converter to convert the analog signals to digital signals, as well as a multiplexer to read the analog signals from multiple channels, a signal conditioner to modify the analog signals from the multiplexer, and an amplifier to amplify the analog signals from the signal conditioner.