公开(公告)号：US20140169885A1

公开(公告)日：2014-06-19

申请号：US14127095

申请日：2012-06-25

申请人： Andy Green ,  Cédric Mouchel

发明人： Andy Green ,  Cédric Mouchel

IPC分类号： F16L1/23 ,  F16L1/12 ,  B63B35/03

CPC分类号： F16L1/12 ,  B63B35/03 ,  F16L1/19 ,  F16L1/203 ,  F16L1/207 ,  F16L1/23

摘要： A marine pipeline-installation tower comprising at least two opposing legs, and one or more tensioning assemblies supported by the opposing legs for surrounding and supporting an intermediate pipeline during installation, at least one of the intermediate tensioning assemblies comprising two or more discrete segments, the segments being moveable between: a closed position wherein the segments are conjoined to form an enclosing pipeline annulus able to support the pipeline between the legs of the tower; and an open position wherein at least two of the segments are disconnected and separate. In this way, a better clearance is achievable between the parts of the segments able to form the enclosing pipeline annulus when the segments are in their open position, because the segments are able to be disconnected and separate despite still being supported within the limited room between the fixed legs of the tower.

摘要翻译： 包括至少两个相对的腿的海上管道安装塔和由相对的腿支撑的一个或多个张紧组件，用于在安装期间围绕和支撑中间管道，至少一个中间张紧组件包括两个或更多个离散段， 段可在下列位置之间移动：闭合位置，其中所述段被结合以形成能够支撑所述塔的腿之间的管道的封闭管道环空; 以及打开位置，其中至少两个段被断开并分离。 以这种方式，当节段处于其打开位置时能够形成封闭的管道环空的段的部分之间可以实现更好的间隙，因为段能够被断开和分离，尽管仍然被支撑在有限的室内 塔的固定腿。

公开(公告)号：US07464192B2

公开(公告)日：2008-12-09

申请号：US10238757

申请日：2002-09-10

申请人： Philip C. Barnett ,  Andy Green ,  Peter C. Van Buskirk

发明人： Philip C. Barnett ,  Andy Green ,  Peter C. Van Buskirk

IPC分类号： G06F3/00

CPC分类号： G06F13/385

摘要： A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.

摘要翻译： 公开了可用于支持多个通信协议的半导体电路中的可编程串行接口。 可编程串行接口包括实现多个通信协议，可选协议特定硬件，处理器和存储器的任务和功能的一个或多个共享硬件组件。 对于支持的通信协议所需的每个任务或功能，确定将使用共享硬件，协议特定硬件或软件来实现功能的哪些部分。 识别要支持的通信协议，并且分析根据每个所支持的协议执行的功能，以识别适合于具有其他通信协议的公共或共享硬件的那些功能。 另外，确定必须以硬件实现的独特或时间关键的功能。 最后，在硬件中未实现的任何功能都是用软件实现的。

公开(公告)号：US11306494B1

公开(公告)日：2022-04-19

申请号：US16579101

申请日：2019-09-23

申请人： Andy Green

发明人： Andy Green

IPC分类号： E04G21/18 ,  F16B2/10

摘要： A string groove masonry clamp having a clamp body with first and second clamp sides pivotally connected together and biased to clamp onto a masonry block to align a string positioning guide having a string groove at the edge of the apex of the corner of the block and an adjustable opposing jaw.

公开(公告)号：US10458132B1

公开(公告)日：2019-10-29

申请号：US15827469

申请日：2017-11-30

申请人： Andy Green

发明人： Andy Green

IPC分类号： E04G21/18 ,  B25B5/04 ,  B25B5/06

摘要： A string groove masonry clamp having a clamp body with first and second clamp sides pivotally connected together and biased to clamp onto a masonry block to align a string positioning guide having a string groove at the edge of the apex of the corner of the block.

公开(公告)号：USD839085S1

公开(公告)日：2019-01-29

申请号：US29599760

申请日：2017-04-06

申请人： Andy Green

设计人： Andy Green

公开(公告)号：US09316332B2

公开(公告)日：2016-04-19

申请号：US14127095

申请日：2012-06-25

申请人： Andy Green ,  Cédric Mouchel

发明人： Andy Green ,  Cédric Mouchel

IPC分类号： F16L1/23 ,  F16L1/12 ,  F16L1/20 ,  F16L1/19 ,  B63B35/03

CPC分类号： F16L1/12 ,  B63B35/03 ,  F16L1/19 ,  F16L1/203 ,  F16L1/207 ,  F16L1/23

摘要： A marine pipeline-installation tower comprising at least two opposing legs, and one or more tensioning assemblies supported by the opposing legs for surrounding and supporting an intermediate pipeline during installation, at least one of the intermediate tensioning assemblies comprising two or more discrete segments, the segments being moveable between: a closed position wherein the segments are conjoined to form an enclosing pipeline annulus able to support the pipeline between the legs of the tower; and an open position wherein at least two of the segments are disconnected and separate. In this way, a better clearance is achievable between the parts of the segments able to form the enclosing pipeline annulus when the segments are in their open position, because the segments are able to be disconnected and separate despite still being supported within the limited room between the fixed legs of the tower.

摘要翻译： 包括至少两个相对的腿的海上管道安装塔和由相对的腿支撑的一个或多个张紧组件，用于在安装期间围绕和支撑中间管道，至少一个中间张紧组件包括两个或更多个离散段， 段可在下列位置之间移动：闭合位置，其中所述段被结合以形成能够支撑所述塔的腿之间的管道的封闭管道环空; 以及打开位置，其中至少两个段被断开并分离。 以这种方式，当节段处于其打开位置时能够形成封闭的管道环空的段的部分之间可以实现更好的间隙，因为段能够被断开和分离，尽管仍然被支撑在有限的室内 塔的固定腿。

公开(公告)号：USD577076S1

公开(公告)日：2008-09-16

申请号：US29305268

申请日：2008-03-17

申请人： Andy Green

设计人： Andy Green

公开(公告)号：US06223144B1

公开(公告)日：2001-04-24

申请号：US09047809

申请日：1998-03-24

申请人： Philip Barnett ,  Andy Green

发明人： Philip Barnett ,  Andy Green

IPC分类号： G06F945

CPC分类号： G06F11/3664

摘要： A microcontroller software testing tool is disclosed for testing and debugging software for a semiconductor circuit. The microcontroller software testing tool includes a simulator for simulating the execution of the software program on the target semiconductor circuit and an emulator to permit emulation before the actual silicon exists. The emulator utilizes the same high definition language specification, such as VHDL models, that define the silicon during the fabrication process plus additional logic to model behavior of the emulated processor. In a simulation mode, the microcontroller software testing tool simulates the target semiconductor circuit on a general purpose computing device, by interpreting the instructions in the software using an instruction set of the target semiconductor circuit, and otherwise behaving like the target semiconductor circuit; and executes and evaluates the software on the simulated semiconductor circuit. The microcontroller software testing tool monitors the estimated time to execute the software on the semiconductor circuit. In an emulation mode, the microcontroller software testing tool utilizes a low-cost field programmable gate array programmed with a hardware description language description of the target semiconductor circuit. The microcontroller software testing tool is accessible by means of a data exchange protocol provided by the operating system. The microcontroller software testing tool preferably provides a modular configuration. The microcontroller software testing tool monitors the percentage of the code that is executed during testing.

摘要翻译： 公开了用于半导体电路的测试和调试软件的微控制器软件测试工具。 微控制器软件测试工具包括用于模拟目标半导体电路上的软件程序的执行的仿真器以及在存在实际的硅之前允许仿真的仿真器。 仿真器利用与制造过程中定义硅的VHDL模型相同的高清晰度语言规范，以及模拟处理器的行为模型的附加逻辑。 在仿真模式中，微控制器软件测试工具通过使用目标半导体电路的指令集解释软件中的指令，并以其他方式像目标半导体电路一样，在通用计算设备上模拟目标半导体电路; 并执行并评估模拟半导体电路上的软件。 微控制器软件测试工具监视在半导体电路上执行软件的估计时间。 在仿真模式下，微控制器软件测试工具利用用目标半导体电路的硬件描述语言描述编程的低成本现场可编程门阵列。 微控制器软件测试工具可以通过操作系统提供的数据交换协议来访问。 微控制器软件测试工具最好提供模块化配置。 微控制器软件测试工具监视在测试期间执行的代码的百分比。

公开(公告)号：USD916703S1

公开(公告)日：2021-04-20

申请号：US29715416

申请日：2019-12-02

申请人： Andy Green

设计人： Andy Green

公开(公告)号：US06639428B2

公开(公告)日：2003-10-28

申请号：US10027665

申请日：2001-12-20

申请人： Andy Green ,  Philip C. Barnett

发明人： Andy Green ,  Philip C. Barnett

IPC分类号： G06F132

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

摘要： A digital circuit run in conjunction with a system clock signal. The digital circuit includes: a digital logic circuitry regulated by a clock signal and powered by a system current; and a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry. The clocking circuitry includes: a power supply monitor circuitry, communicatively coupled to the power supply, providing a first signal indicative of a predetermined level of system current; and a clock regulation circuitry, communicatively coupled to the power supply circuitry, which outputs the clock signal to the digital logic circuitry in response to the first signal. The clock signal comprises (1) the system clock signal when the first signal is in a first state, and (2) a modified clock signal when the first signal is in a second state.

摘要翻译： 数字电路与系统时钟信号一起运行。 数字电路包括：由时钟信号调节并由系统电流供电的数字逻辑电路; 以及通信地耦合到数字逻辑电路和系统时钟信号的时钟电路，用于将时钟信号提供给数字逻辑电路。 时钟电路包括：电源监视器电路，通信地耦合到电源，提供指示系统电流的预定电平的第一信号; 以及通信地耦合到电源电路的时钟调节电路，其响应于第一信号将时钟信号输出到数字逻辑电路。 时钟信号包括（1）当第一信号处于第一状态时的系统时钟信号，和（2）当第一信号处于第二状态时的修改的时钟信号。