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公开(公告)号：US20050200629A1
公开(公告)日：2005-09-15
申请号：US11117863
申请日：2005-04-29
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中
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公开(公告)号：US20070285427A1
公开(公告)日：2007-12-13
申请号：US11842256
申请日：2007-08-21
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中
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公开(公告)号：US20100231592A1
公开(公告)日：2010-09-16
申请号：US12791597
申请日：2010-06-01
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中
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公开(公告)号：US07327369B2
公开(公告)日：2008-02-05
申请号：US11117863
申请日：2005-04-29
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中
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公开(公告)号：US20050110792A1
公开(公告)日：2005-05-26
申请号：US10718318
申请日：2003-11-20
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中
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公开(公告)号：US06897871B1
公开(公告)日：2005-05-24
申请号：US10718318
申请日：2003-11-20
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
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公开(公告)号：US20110216077A1
公开(公告)日：2011-09-08
申请号：US13109738
申请日：2011-05-17
申请人： Stephen Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Stephen Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中
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