公开(公告)号：US20110216077A1

公开(公告)日：2011-09-08

申请号：US13109738

申请日：2011-05-17

申请人： Stephen Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Stephen Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00 ,  G06T1/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US20050200629A1

公开(公告)日：2005-09-15

申请号：US11117863

申请日：2005-04-29

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06T15/60 ,  G06T15/50 ,  G09G5/36

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US20070285427A1

公开(公告)日：2007-12-13

申请号：US11842256

申请日：2007-08-21

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US20100231592A1

公开(公告)日：2010-09-16

申请号：US12791597

申请日：2010-06-01

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00 ,  G06T15/50

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US07327369B2

公开(公告)日：2008-02-05

申请号：US11117863

申请日：2005-04-29

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06F15/00 ,  G06T1/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US20050110792A1

公开(公告)日：2005-05-26

申请号：US10718318

申请日：2003-11-20

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06T1/00 ,  G06F15/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

摘要翻译： 公开了一种采用单一着色器的图形处理架构。 该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一 多个输入之一。 着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器 在音序器中

公开(公告)号：US06897871B1

公开(公告)日：2005-05-24

申请号：US10718318

申请日：2003-11-20

申请人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

发明人： Steven Morein ,  Laurent Lefebvre ,  Andy Gruber ,  Andi Skende

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06F15/00 ,  G06T1/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

公开(公告)号：US06720964B1

公开(公告)日：2004-04-13

申请号：US09457648

申请日：1999-12-09

申请人： Mark C. Fowler ,  Stephen Morein ,  Andi Skende ,  Kevin M. Olson

发明人： Mark C. Fowler ,  Stephen Morein ,  Andi Skende ,  Kevin M. Olson

IPC分类号： G06T1540

CPC分类号： G06T15/405

摘要： A method and apparatus for processing portions of primitives that are being rendered is presented. Primitives that are received are divided into portions that correspond to pixel blocks of the frame. The frame includes a plurality of pixel blocks where each of the pixel blocks includes a plurality of pixels that are included in the frame. Thus, the pixel blocks divide the frame into a number of smaller blocks. A representative Z value for each portion of the primitive is determined, and the representative Z value for the portion of the primitive is compared with a representative buffered Z, which may be the representative buffer Z value for the pixel block to which the portion corresponds. If the representative Z value for the portion compares favorably with the representative buffered Z value such that the portion is determined to lie completely behind the information currently stored for that pixel block, the portion is discarded. If the representative Z value for the portion compares with the representative buffer Z value in such a way that not all of the portion is ensured of being positioned behind currently buffered data for the pixel block, the portion of the primitive is processed further such that pixel fragments corresponding to the portion are generated and combined with the information currently stored for that pixel block. The representative buffered Z values for each of the pixel blocks may be derived based on a compression scheme applied to the Z values for each of the individual pixel blocks.

摘要翻译： 呈现用于处理正在呈现的图元的部分的方法和装置。 被接收的原语被分成对应于帧的像素块的部分。 该帧包括多个像素块，其中每个像素块包括包括在帧中的多个像素。 因此，像素块将帧划分成多个较小的块。 确定基元的每个部分的代表性的Z值，并将原始部分的代表Z值与代表性的缓冲Z进行比较，代表性的缓冲Z可以是该部分对应的像素块的代表性缓冲器Z值。 如果该部分的代表Z值与代表性缓冲的Z值相比有利地被确定为完全落在当前为该像素块存储的信息之后，则该部分被丢弃。 如果该部分的代表Z值与代表性缓冲器Z值相比较，使得不保证所有部分都被定位在像素块的当前缓冲数据的后面，则进一步处理原语的该部分，使得像素 产生与该部分相对应的片段，并与当前为该像素块存储的信息组合。 可以基于应用于每个像素块的Z值的压缩方案来导出每个像素块的代表性缓冲的Z值。

公开(公告)号：US08760454B2

公开(公告)日：2014-06-24

申请号：US13109738

申请日：2011-05-17

申请人： Stephen L. Morein ,  Laurent Lefebvre ,  Andrew E. Gruber ,  Andi Skende

发明人： Stephen L. Morein ,  Laurent Lefebvre ,  Andrew E. Gruber ,  Andi Skende

IPC分类号： G06F15/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/80

摘要： A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

摘要翻译： 一个示例中的图形处理架构通过将顶点数据发送到通用寄存器块来执行顶点操作操作和像素操作操作，并且对顶点数据ba处理器执行顶点操作，除非通用寄存器块在其中没有足够的可用空间 存储传入的顶点数据; 并且继续基于在指令存储器中保持的指令来处理或正在执行处理器的像素计算操作，直到通用寄存器块中的足够的寄存器变得可用为止。