公开(公告)号：US06200887B1

公开(公告)日：2001-03-13

申请号：US09490133

申请日：2000-01-24

申请人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

发明人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

IPC分类号： H01L214763

CPC分类号： H01L21/28105 ,  H01L21/28123 ,  H01L21/28247 ,  H01L21/31662

摘要： A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate. Thereafter, the amorphized silicon is then removed by an anisotropic etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask completing the gate structure having smooth sidewalls.

摘要翻译： 描述了通过沿着栅极边界使多晶硅非晶化来形成具有平滑侧壁的栅极结构的方法。 这种方法导致最小的栅极耗尽效应和较小器件的栅极中的改进的临界尺寸控制。 该方法包括在半导体衬底的表面上提供栅极氧化硅层。 在栅极氧化硅上沉积诸如多晶硅的栅极电极层，随后沉积在栅极电极层上的掩模氧化物层。 图案化掩模氧化物层以形成栅电极。 硅或锗的离子注入对未被掩模氧化物掩模保护的多晶硅区域进行非晶化，并且使沿多晶硅栅极边界的区域非晶化。 此后，通过各向异性蚀刻去除非晶化硅，在掩模氧化物掩模的边缘下方的栅极电极侧壁上留下非晶形硅的窄区域，从而完成具有平滑侧壁的栅极结构。