公开(公告)号：US06200887B1

公开(公告)日：2001-03-13

申请号：US09490133

申请日：2000-01-24

申请人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

发明人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

IPC分类号： H01L214763

CPC分类号： H01L21/28105 ,  H01L21/28123 ,  H01L21/28247 ,  H01L21/31662

摘要： A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate. Thereafter, the amorphized silicon is then removed by an anisotropic etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask completing the gate structure having smooth sidewalls.

摘要翻译： 描述了通过沿着栅极边界使多晶硅非晶化来形成具有平滑侧壁的栅极结构的方法。 这种方法导致最小的栅极耗尽效应和较小器件的栅极中的改进的临界尺寸控制。 该方法包括在半导体衬底的表面上提供栅极氧化硅层。 在栅极氧化硅上沉积诸如多晶硅的栅极电极层，随后沉积在栅极电极层上的掩模氧化物层。 图案化掩模氧化物层以形成栅电极。 硅或锗的离子注入对未被掩模氧化物掩模保护的多晶硅区域进行非晶化，并且使沿多晶硅栅极边界的区域非晶化。 此后，通过各向异性蚀刻去除非晶化硅，在掩模氧化物掩模的边缘下方的栅极电极侧壁上留下非晶形硅的窄区域，从而完成具有平滑侧壁的栅极结构。

公开(公告)号：US06468853B1

公开(公告)日：2002-10-22

申请号：US09641389

申请日：2000-08-18

申请人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

发明人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

IPC分类号： H01L218238

CPC分类号： H01L21/76235

摘要： A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning elements. After trench etch, a thin conformal layer of either amorphous, epitaxial or polysilicon is deposited over the silicon nitride and within the trench and annealed. Where the silicon has been deposited on the silicon bottom and sides of the open trench, the annealing effectively forms a single crystal or epitaxial silicon. Next a silicon oxide liner is grown over the conformal silicon layer. The trench is then filled with silicon oxide, the structure is planarized by either chemical mechanical polishing or etching, and the nitride and pad oxide is removed This leaves a polysilicon film on the vertical edges of the filler oxide which extends slightly above the surface of the silicon substrate. A thermal oxidation step is performed converting the poly film into silicon oxide which slightly extends the STI field oxide into the active device region eliminating any reduced oxide coverage or oxide recesses in the corner regions.

摘要翻译： 描述了在浅沟槽隔离结构的角上制造具有改善的氧化物覆盖的半导体器件的结构和工艺。 使用衬垫氧化物和氮化硅层作为图案化元件来蚀刻STI沟槽。 在沟槽蚀刻之后，非晶，外延或多晶硅的薄的共形层沉积在氮化硅上并在沟槽内并退火。 当硅沉积在开口沟槽的硅底部和侧面上时，退火有效地形成单晶或外延硅。 接下来，在保形硅层上生长氧化硅衬垫。 然后用氧化硅填充沟槽，通过化学机械抛光或蚀刻对该结构进行平面化，并且去除氮化物和衬垫氧化物。在填充氧化物的垂直边缘上留下多晶硅膜，其在 硅衬底。 执行热氧化步骤，将多晶硅膜转化为将STI场氧化物稍微延伸到有源器件区域中的氧化硅，消除角区域中任何减少的氧化物覆盖或氧化物凹陷。

公开(公告)号：US08236595B2

公开(公告)日：2012-08-07

申请号：US12376993

申请日：2006-08-11

申请人： Ajay Agarwal ,  Navab Singh ,  Rakesh Kumar ,  Ieng Kin Lao ,  Narayanan Balasubramanian

发明人： Ajay Agarwal ,  Navab Singh ,  Rakesh Kumar ,  Ieng Kin Lao ,  Narayanan Balasubramanian

IPC分类号： H01L21/00

CPC分类号： B01J19/0046 ,  B01J2219/00497 ,  B01J2219/00527 ,  B01J2219/00585 ,  B01J2219/00596 ,  B01J2219/00612 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01J2219/00677 ,  B01J2219/00722 ,  B01J2219/00725 ,  B01J2219/00729 ,  B81B2201/0214 ,  B81B2203/0338 ,  B81B2207/07 ,  B81C1/00119 ,  B82Y15/00 ,  C40B60/12 ,  Y10S977/957 ,  Y10S977/958

摘要： A method of fabricating a sensor comprising a nanowire on a support substrate with a first semiconductor layer arranged on the support substrate is disclosed. The method comprises forming a fin structure from the first semiconductor layer, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing at least the fin portion of the fin structure thereby forming the nanowire being surrounded by a first layer of oxide; and forming an insulating layer above the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. A nanowire sensor is also disclosed. The nanowire sensor comprises a support substrate, a semiconducting fin structure arranged on the support substrate, the fin structure comprising at least two semiconducting supporting portions and a nanowire arranged there between; and a first insulating layer on a contact surface of the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel.

摘要翻译： 公开了一种制造包括在支撑衬底上的纳米线的传感器的方法，其中第一半导体层布置在支撑衬底上。 该方法包括从第一半导体层形成翅片结构，鳍结构包括至少两个支撑部分和布置在其间的翅片部分; 至少氧化翅片结构的翅片部分，从而形成由第一氧化物层包围的纳米线; 以及在所述支撑部分上方形成绝缘层; 其中所述支撑部分和所述第一绝缘层形成微流体通道。 还公开了一种纳米线传感器。 纳米线传感器包括支撑衬底，布置在支撑衬底上的半导体翅片结构，鳍结构包括至少两个半导电支撑部分和布置在其上的纳米线; 以及在所述支撑部分的接触表面上的第一绝缘层; 其中所述支撑部分和所述第一绝缘层形成微流体通道。

公开(公告)号：US5767004A

公开(公告)日：1998-06-16

申请号：US635992

申请日：1996-04-22

申请人： Narayanan Balasubramanian ,  Ching Win Kong ,  Chuck Jang

发明人： Narayanan Balasubramanian ,  Ching Win Kong ,  Chuck Jang

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L29/49

CPC分类号： H01L21/28061 ,  H01L21/32055 ,  H01L29/4925 ,  H01L29/4933

摘要： A method for forming within an integrated circuit a low impurity diffusion polysilicon layer. Formed upon a semiconductor substrate is an amorphous silicon layer. Formed also upon the semiconductor substrate and contacting the amorphous silicon layer is a polysilicon layer. The amorphous silicon layer and the polysilicon layer are then simultaneously annealed to form a low impurity diffusion polysilicon layer. The low impurity diffusion polysilicon layer is a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties. Optionally, a metal silicide layer may be formed upon the amorphous silicon layer and the polysilicon layer either prior to or subsequent to annealing the amorphous silicon layer and the polysilicon layer. The metal silicide layer and low impurity diffusion polysilicon layer may then be patterned to form a polycide gate electrode.

摘要翻译： 一种在集成电路内形成低杂质扩散多晶硅层的方法。 形成在半导体衬底上的是非晶硅层。 形成在半导体衬底上并与非晶硅层接触的是多晶硅层。 然后，非晶硅层和多晶硅层同时退火以形成低杂质扩散多晶硅层。 低杂质扩散多晶硅层是具有晶界不匹配多晶性质的多晶硅多层。 可选地，在非晶硅层和多晶硅层退火之前或之后，可以在非晶硅层和多晶硅层上形成金属硅化物层。 然后可以对金属硅化物层和低杂质扩散多晶硅层进行构图以形成多晶硅栅极电极。

公开(公告)号：US20100055673A1

公开(公告)日：2010-03-04

申请号：US12303112

申请日：2006-05-31

申请人： Ajay Agarwal ,  Narayanan Balasubramanian ,  Lihui Guo ,  Chee Chung Wong

发明人： Ajay Agarwal ,  Narayanan Balasubramanian ,  Lihui Guo ,  Chee Chung Wong

IPC分类号： C12Q1/70 ,  C12M1/34 ,  B05D3/00 ,  G01N33/53 ,  G01N27/00 ,  B01L3/00

CPC分类号： B81B1/00 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2300/12 ,  B81B2201/058 ,  G01N33/48728 ,  G01N2021/0346 ,  G01N2035/00158 ,  Y10T436/143333

摘要： A device for analysing the status of a biological entity. The device (10) comprises a substantially transparent base substrate (11) having a recess defined therein by at least two opposing lateral walls and a base wall, a substantially transparent filler member (14) having at least a portion thereof occupying the recess, a substantially transparent separation layer (12) disposed between the filler member and the base substrate, and a channel (16) defined in the filler member, wherein the channel comprises an inlet and an outlet, the inlet being arranged on a first lateral wall of the filler member, and the outlet being arranged on a second lateral wall of the filler member, said first lateral wall of the filler member being arranged in opposing relationship with the second lateral wall of the filler member, and at least a portion of the first and the second lateral walls of the filler member being at least substantially perpendicular to the opposing lateral walls defining the recess.

摘要翻译： 用于分析生物实体状态的装置。 装置（10）包括基本上透明的基底（11），其具有通过至少两个相对的侧壁和底壁限定的凹部，基本上透明的填充构件（14），其至少部分占据凹部， 设置在填充构件和基底衬底之间的基本上透明的分离层（12）和限定在填充构件中的通道（16），其中通道包括入口和出口，入口布置在第一侧壁 填料构件，并且出口布置在填料构件的第二侧壁上，填料构件的所述第一侧壁与填料构件的第二侧壁相对置，并且第一和第二侧壁的至少一部分 填充构件的第二侧壁至少基本上垂直于限定凹部的相对侧壁。

公开(公告)号：US07439165B2

公开(公告)日：2008-10-21

申请号：US11100206

申请日：2005-04-06

申请人： Patrick Guo Oiang Lo ,  Lakshmi Kanta Bera ,  Wei Yip Loh ,  Balakumar Subramanian ,  Narayanan Balasubramanian

发明人： Patrick Guo Oiang Lo ,  Lakshmi Kanta Bera ,  Wei Yip Loh ,  Balakumar Subramanian ,  Narayanan Balasubramanian

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78687

摘要： A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration.

摘要翻译： 已经开发了用于形成拉伸和压缩应变硅层以适应MOSFET或CMOS器件的沟道区的工艺。 在形成浅沟槽隔离结构以及施加高温氧化和激活程序之后，开始用于获得应变硅层的制造顺序。 沉积半导体合金层，然后沉积氧化工序，将锗组分从上覆的半导体合金层分离成下面的单晶硅体。 分离到下面的单晶硅体中的锗的水平决定了随后选择性生长的硅层的拉伸状态的应变水平。 本发明的第二个实施方案的特征在于在氧化过程之前使半导体合金层的一部分变薄，允许较低水平的锗分离成下面的单晶硅体的第一下面部分，同时在相同的氧化过程 底层单晶硅体的第二部分接受较高水平的锗分离。 因此，随后沉积的硅 - 锗层，尽管相同的工艺和厚度，可以根据不同的下层部分的锗浓度在不同的状态（拉伸或压缩）和水平应变。

公开(公告)号：US20060199321A1

公开(公告)日：2006-09-07

申请号：US11071768

申请日：2005-03-03

申请人： Patrick Guo Lo ,  Wei Loh ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian

发明人： Patrick Guo Lo ,  Wei Loh ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian

IPC分类号： H01L21/336

CPC分类号： H01L29/78621 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78636

摘要： A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

摘要翻译： 描述了一种形成具有完全硅化栅电极和完全硅化的凸起S / D元件的MOSFET，其几乎共面以在形成与硅化物区域的接触时允许更宽的工艺裕度。 在STI区域上形成绝缘体阻挡层，并且在绝缘体阻挡层和有源区上设置诸如Ti / TiN的共形硅化停止层。 多晶硅层沉积在硅化终止层上，并通过CMP工艺平坦化以形成凸起的S / D元件。 去除栅电极上的氧化物硬掩模以在间隔件之间产生轻微的凹陷。 硅化工艺产生栅电极和由NiSi组成的升高的S / D元件。 可选地，在绝缘体块掩模和间隔物之间​​的衬底中形成凹部，并且使用肖特基势垒代替硅化阻挡层以形成肖特基势垒MOSFET。

公开(公告)号：US06551937B2

公开(公告)日：2003-04-22

申请号：US09938042

申请日：2001-08-23

申请人： Cai Jun ,  Ren Chang Hong ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian ,  Yung Chii Liang

发明人： Cai Jun ,  Ren Chang Hong ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian ,  Yung Chii Liang

IPC分类号： H01L21311

CPC分类号： H01L29/7835 ,  H01L21/76208 ,  H01L21/7624 ,  H01L29/0653 ,  H01L29/66659

摘要： A process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.

摘要翻译： 描述了用于部分SOI结构的掩埋氧化物层的制造方法。 该过程开始于将深沟槽蚀刻成硅体。 对于表面下方的预选深度，沟槽的内壁被保护，然后进行所述壁的氧化，直到在沟槽内部以及沟槽之间的材料发生夹断。 结果是一个连续的维度层，其尺寸和形状由沟槽的数量和位置决定。 本方法还应用于部分SOI RFLDMOS结构的制造以及所得到的器件的性能数据。

公开(公告)号：US07682914B2

公开(公告)日：2010-03-23

申请号：US11981496

申请日：2007-10-30

申请人： Patrick Guo Qiang Lo ,  Wei Yip Loh ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian

发明人： Patrick Guo Qiang Lo ,  Wei Yip Loh ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian

IPC分类号： H01L21/336

CPC分类号： H01L29/78621 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78636

摘要： A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

摘要翻译： 描述了一种形成具有完全硅化栅电极和完全硅化的凸起S / D元件的MOSFET，该S / D元件几乎共面以在形成与硅化物区域的接触时允许更宽的工艺裕度。 在STI区域上形成绝缘体阻挡层，并且在绝缘体阻挡层和有源区上设置诸如Ti / TiN的共形硅化停止层。 多晶硅层沉积在硅化终止层上，并通过CMP工艺平坦化以形成凸起的S / D元件。 去除栅电极上的氧化物硬掩模以在间隔件之间产生轻微的凹陷。 硅化工艺产生栅电极和由NiSi组成的升高的S / D元件。 可选地，在绝缘体块掩模和间隔物之间​​的衬底中形成凹部，并且使用肖特基势垒代替硅化阻挡层以形成肖特基势垒MOSFET。

公开(公告)号：US20060226483A1

公开(公告)日：2006-10-12

申请号：US11100206

申请日：2005-04-06

申请人： Patrick Lo ,  Lakshmi Bera ,  Wei Loh ,  Balakumar Subramanian ,  Narayanan Balasubramanian

发明人： Patrick Lo ,  Lakshmi Bera ,  Wei Loh ,  Balakumar Subramanian ,  Narayanan Balasubramanian

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78687

摘要： A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration.

摘要翻译： 已经开发了用于形成拉伸和压缩应变硅层以适应MOSFET或CMOS器件的沟道区的工艺。 在形成浅沟槽隔离结构以及施加高温氧化和激活程序之后，开始用于获得应变硅层的制造顺序。 沉积半导体合金层，然后沉积氧化工序，将锗组分从上覆的半导体合金层分离成下面的单晶硅体。 分离到下面的单晶硅体中的锗的水平决定了随后选择性生长的硅层的拉伸状态的应变水平。 本发明的第二个实施方案的特征在于在氧化过程之前使半导体合金层的一部分变薄，允许较低水平的锗分离成下面的单晶硅体的第一下面部分，同时在相同的氧化过程 底层单晶硅体的第二部分接受较高水平的锗分离。 因此，随后沉积的硅 - 锗层，尽管相同的工艺和厚度，可以根据不同的下层部分的锗浓度在不同的状态（拉伸或压缩）和水平应变。