公开(公告)号：US06200887B1

公开(公告)日：2001-03-13

申请号：US09490133

申请日：2000-01-24

申请人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

发明人： Palanivel Balasubramaniam ,  Narayanan Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Arjun Kantimahanti

IPC分类号： H01L214763

CPC分类号： H01L21/28105 ,  H01L21/28123 ,  H01L21/28247 ,  H01L21/31662

摘要： A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate. Thereafter, the amorphized silicon is then removed by an anisotropic etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask completing the gate structure having smooth sidewalls.

摘要翻译： 描述了通过沿着栅极边界使多晶硅非晶化来形成具有平滑侧壁的栅极结构的方法。 这种方法导致最小的栅极耗尽效应和较小器件的栅极中的改进的临界尺寸控制。 该方法包括在半导体衬底的表面上提供栅极氧化硅层。 在栅极氧化硅上沉积诸如多晶硅的栅极电极层，随后沉积在栅极电极层上的掩模氧化物层。 图案化掩模氧化物层以形成栅电极。 硅或锗的离子注入对未被掩模氧化物掩模保护的多晶硅区域进行非晶化，并且使沿多晶硅栅极边界的区域非晶化。 此后，通过各向异性蚀刻去除非晶化硅，在掩模氧化物掩模的边缘下方的栅极电极侧壁上留下非晶形硅的窄区域，从而完成具有平滑侧壁的栅极结构。

公开(公告)号：US06312999B1

公开(公告)日：2001-11-06

申请号：US09819378

申请日：2001-03-29

申请人： Subrahamanyam Chivukula ,  Yelehanka Ramachandramurthy Pradeep ,  Madhusudan Mukhopdhyay ,  Palanivel Balasubramaniam

发明人： Subrahamanyam Chivukula ,  Yelehanka Ramachandramurthy Pradeep ,  Madhusudan Mukhopdhyay ,  Palanivel Balasubramaniam

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/7833

摘要： A method for forming a MOSFET having an LDD structure with minimal lateral dopant diffusion is described. A gate electrode is provided overlying a gate dielectric layer on a semiconductor substrate. Dielectric spacers are formed on sidewalls of the gate electrode. Source and drain regions are formed associated with the gate electrode. The gate electrode and source and drain regions are silicided. Thereafter, the spacers are removed to expose the semiconductor substrate. LDD regions are formed using plasma doping in the exposed semiconductor substrate between the source and drain regions and the gate electrode to complete formation of an LDD structure in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种用于形成具有最小横向掺杂剂扩散的LDD结构的MOSFET的方法。 栅电极被设置在半导体衬底上的栅介电层上。 电介质隔板形成在栅电极的侧壁上。 源极和漏极区域形成为与栅电极相关联。 栅电极和源极和漏极区域被硅化。 此后，去除间隔物以露出半导体衬底。 在源极和漏极区域和栅电极之间的暴露的半导体衬底中使用等离子体掺杂形成LDD区域，以在集成电路器件的制造中完成LDD结构的形成。

公开(公告)号：US06468853B1

公开(公告)日：2002-10-22

申请号：US09641389

申请日：2000-08-18

申请人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

发明人： Palanivel Balasubramanian ,  Yelehanka Ramachandramurthy Pradeep ,  Chivkula Subrahmanyam ,  Narayanan Balasubramanian

IPC分类号： H01L218238

CPC分类号： H01L21/76235

摘要： A structure and a process for manufacturing semiconductor devices with improved oxide coverage on the corners of a shallow trench isolation structure is described. The STI trench is etched using a pad oxide and silicon nitride layers as patterning elements. After trench etch, a thin conformal layer of either amorphous, epitaxial or polysilicon is deposited over the silicon nitride and within the trench and annealed. Where the silicon has been deposited on the silicon bottom and sides of the open trench, the annealing effectively forms a single crystal or epitaxial silicon. Next a silicon oxide liner is grown over the conformal silicon layer. The trench is then filled with silicon oxide, the structure is planarized by either chemical mechanical polishing or etching, and the nitride and pad oxide is removed This leaves a polysilicon film on the vertical edges of the filler oxide which extends slightly above the surface of the silicon substrate. A thermal oxidation step is performed converting the poly film into silicon oxide which slightly extends the STI field oxide into the active device region eliminating any reduced oxide coverage or oxide recesses in the corner regions.

摘要翻译： 描述了在浅沟槽隔离结构的角上制造具有改善的氧化物覆盖的半导体器件的结构和工艺。 使用衬垫氧化物和氮化硅层作为图案化元件来蚀刻STI沟槽。 在沟槽蚀刻之后，非晶，外延或多晶硅的薄的共形层沉积在氮化硅上并在沟槽内并退火。 当硅沉积在开口沟槽的硅底部和侧面上时，退火有效地形成单晶或外延硅。 接下来，在保形硅层上生长氧化硅衬垫。 然后用氧化硅填充沟槽，通过化学机械抛光或蚀刻对该结构进行平面化，并且去除氮化物和衬垫氧化物。在填充氧化物的垂直边缘上留下多晶硅膜，其在 硅衬底。 执行热氧化步骤，将多晶硅膜转化为将STI场氧化物稍微延伸到有源器件区域中的氧化硅，消除角区域中任何减少的氧化物覆盖或氧化物凹陷。

公开(公告)号：US20090108257A1

公开(公告)日：2009-04-30

申请号：US11927658

申请日：2007-10-29

申请人： Hai Cong ,  Yan San Li ,  Chun Hui Low ,  Yelehanka Ramachandramurthy Pradeep ,  Liang Choo Hsia

发明人： Hai Cong ,  Yan San Li ,  Chun Hui Low ,  Yelehanka Ramachandramurthy Pradeep ,  Liang Choo Hsia

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

摘要翻译： 包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。 沟槽形成在IC的外围，用作保护环。

公开(公告)号：US06726545B2

公开(公告)日：2004-04-27

申请号：US10134821

申请日：2002-04-26

申请人： Subramanian Balakumar ,  Chen Feng ,  Victor Lim ,  Paul Proctor ,  Mukhopadhyay Madhusudan ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

发明人： Subramanian Balakumar ,  Chen Feng ,  Victor Lim ,  Paul Proctor ,  Mukhopadhyay Madhusudan ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： B24B100

CPC分类号： B24B37/16 ,  B24B21/10 ,  B24B37/245

摘要： A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.

摘要翻译： 一种用于抛光包括具有形成连续环的至少两个抛光带的新型抛光带装置的半导体衬底的线性抛光装置。 每个带具有外部抛光表面和内部光滑表面。 皮带沿着彼此间隔开，在每一端共享公共轴线。 皮带环绕一对辊组成一端的驱动辊和另一端的从动辊。 压板构件插入每个带并且放置在成对的辊之间。 压板提供抛光平面和抛光带的支撑表面。 抛光平面包括与平面下方的细长的增压室连通的多个孔。 该室供应压缩气体以向抛光带施加向上的压力。 驱动辊连接到单独的马达以独立地驱动和控制至少所述两个抛光带。

公开(公告)号：US06468877B1

公开(公告)日：2002-10-22

申请号：US09907651

申请日：2001-07-19

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

IPC分类号： H01L2176

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

摘要翻译： 一种制造半导体器件的气隙间隔物的方法，包括以下步骤。 提供具有至少一对限定有源区域的STI的半导体衬底。 在有源区内的基板上形成栅电极。 栅电极具有底层栅介电层。 在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。 在衬垫氧化物层上形成衬里氮化物层。 在结构上形成厚的氧化物层。 厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。 用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。 在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。 蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。 栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

公开(公告)号：US06455377B1

公开(公告)日：2002-09-24

申请号：US09765040

申请日：2001-01-19

申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/1054 ,  H01L29/66916 ,  H01L29/7827 ,  H01L29/802

摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

摘要翻译： 一种制造垂直沟道晶体管的方法，包括以下步骤。 提供具有上表面的半导体衬底。 在半导体衬底上形成高掺杂N型下部外延硅层。 在下部外延硅层上形成低掺杂P型中间外延硅层。 在中间外延硅层上形成高掺杂N型上部外延硅层。 蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。 在隔离槽内形成氧化物。 氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。 在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。 在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。 栅极导体层形成在栅极电介质层上，填充栅极沟槽。

公开(公告)号：US06440800B1

公开(公告)日：2002-08-27

申请号：US09769814

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/365 ,  H01L29/7827

摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

公开(公告)号：US06399448B1

公开(公告)日：2002-06-04

申请号：US09443426

申请日：1999-11-19

申请人： Madhusudan Mukhopadhyay ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

发明人： Madhusudan Mukhopadhyay ,  Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： A method for forming a multiple thickness gate oxide layer by implanting nitrogen ions in a first area of a semiconductor substrate while a second area of the semiconductor substrate is masked; implanting argon ions into the second area of the semiconductor substrate while the first area of the semiconductor substrate is masked; and thermally growing a gate oxide layer wherein, the oxide growth is retarded in the first area and enhanced in the second area. A threshold voltage implant and/or an anti-punchthrough implant can optionally be implanted into the semiconductor substrate prior to the nitrigen implant using the same implant mask as the nitrogen implant for a low voltage gate, and prior to the argon implant using the same implant mask as the argonm implant for a high voltage gate, further reducing processing steps.

摘要翻译： 一种在半导体衬底的第二区域被掩蔽的同时，在半导体衬底的第一区域中注入氮离子形成多层栅极氧化层的方法; 在半导体衬底的第一区域被掩蔽时将氩离子注入到半导体衬底的第二区域中; 并且热生长栅极氧化物层，其中氧化物生长在第一区域中延迟并在第二区域增强。 在使用与用于低电压栅极的氮注入相同的注入掩模的氮掺杂之前，以及在使用相同植入物的氩注入之前，可以可选地将阈值电压注入和/或抗穿透注入注入到半导体衬底中 掩模作为高压栅极的氩离子注入，进一步减少加工步骤。

公开(公告)号：US06316304B1

公开(公告)日：2001-11-13

申请号：US09614553

申请日：2000-07-12

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Tjin Tjin Tjoa ,  Kelvin Wei Loong Loh

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jie Yu ,  Tjin Tjin Tjoa ,  Kelvin Wei Loong Loh

IPC分类号： H01L218238

CPC分类号： H01L21/8238 ,  H01L21/823468

摘要： A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface. The result is a thicker oxide in the areas protected by the mask during the previous etch step. The oxide is anisotropically etched and spacers are formed along the gate sidewalls. The spacers are wider in the areas with the thicker oxide. The process continues by etching the etch stop layer not protected by the spacers. The source and drain electrodes are then formed by implanting ions into the substrate not protected by the gate structure and sidewall spacers. Adjustment of the spacer width is accomplished by adjusting the total thickness of the etch stop and spacer oxide layers. Spacer width variation is controlled by changing the deposition thickness of the first spacer oxide layer.

摘要翻译： 描述了形成具有不同宽度的栅极侧壁间隔物的方法。 间隔宽度的变化允许通过改变轻掺杂源极/漏极延伸部分的尺寸来优化MOSFET特性。 该方法使用其中通过常规技术在衬底上形成包括栅电极和栅极氧化物的栅极结构的方法来实现。 轻掺杂的源极漏极延伸部被注入到不被栅极结构保护的衬底中。 然后用绝缘衬垫层覆盖暴露的衬底和栅极结构。 之后是绝缘衬垫层上的蚀刻停止层沉积。 然后在蚀刻停止层上沉积第一间隔氧化物层。 掩蔽需要较厚间隔物的区域，并且去除未掩蔽的间隔氧化物层。 然后剥去掩模，并在整个表面上生长附加的间隔氧化物。 结果是在先前蚀刻步骤期间由掩模保护的区域中较厚的氧化物。 氧化物被各向异性蚀刻，并且沿着栅极侧壁形成间隔物。 在具有较厚氧化物的区域中，间隔物较宽。 该过程通过蚀刻不被间隔物保护的蚀刻停止层而继续。 然后通过将离子注入到不被栅极结构和侧壁间隔物保护的衬底中来形成源极和漏极。 通过调整蚀刻停止层和间隔氧化物层的总厚度来实现间隔物宽度的调整。 通过改变第一间隔氧化物层的沉积厚度来控制间隔宽度变化。