公开(公告)号：US08806089B2

公开(公告)日：2014-08-12

申请号：US13723380

申请日：2012-12-21

Applicant: Andrew Li ,  Michael Lau ,  Asad Khamisy

Inventor： Andrew Li ,  Michael Lau ,  Asad Khamisy

IPC: G06F3/00

CPC classification number: H04L49/9057 ,  G06F9/3004 ,  H04L47/52 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9047

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract translation: 交通管理器包括执行单元，其响应于与存储器中的数据排队相关的指令。 指令可以由网络处理器提供，该网络处理器被编程为根据数据生成这样的指令。 这种指令的示例包括（1）不链接到队列的数据单元（固定大小或可变大小）的写入，（2）数据单元相对于彼此的重排序而不移动存储器中的数据单元，以及（ 3）将先前写入的数据单元链接到队列。 网络处理器和流量管理器可以在单个芯片中实现。

公开(公告)号：US20080320485A1

公开(公告)日：2008-12-25

申请号：US12201385

申请日：2008-08-29

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/383 ,  G06F9/52

Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Abstract translation: 基于一个或多个路径的初始确定，协处理器（提供到存储器的接口）中的逻辑（也称为“同步逻辑”）从多个任务中的每一个接收信号（称为“声明”） （也称为“代码路径”）在任务可能遵循的指令流（例如源自高级软件程序或低级微代码）中。 一旦任务（也被称为“禁用”任务）声明其缺少访问共享数据的需要，同步逻辑允许共享数据被其他指示（也称为“需要”的任务）访问，这些任务已经表明了他们的需要 访问相同。 此外，同步逻辑还允许在当前任务完成对共享数据的访问时由其他有需要的任务访问共享数据（假设当前任务也是有需要的任务）。

公开(公告)号：US08001547B2

公开(公告)日：2011-08-16

申请号：US12201385

申请日：2008-08-29

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F9/46 ,  G06F12/00

CPC classification number: G06F9/3851 ,  G06F9/383 ,  G06F9/52

Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Abstract translation: 基于一个或多个路径的初始确定，协处理器（提供到存储器的接口）中的逻辑（也称为“同步逻辑”）从多个任务中的每一个接收信号（称为“声明”） （也称为“代码路径”）在任务可能遵循的指令流（例如源自高级软件程序或低级微代码）中。 一旦任务（也被称为“禁用”任务）声明其缺少访问共享数据的需要，同步逻辑允许共享数据被其他指示（也称为“需要”的任务）访问，这些任务已经表明了他们的需要 访问相同。 此外，同步逻辑还允许在当前任务完成对共享数据的访问时由其他有需要的任务访问共享数据（假设当前任务也是有需要的任务）。

公开(公告)号：US07558890B1

公开(公告)日：2009-07-07

申请号：US10741132

申请日：2003-12-19

Applicant: Andrew Li ,  Michael Lau ,  Asad Khamisy

Inventor： Andrew Li ,  Michael Lau ,  Asad Khamisy

IPC: G06F3/00

CPC classification number: H04L49/9057 ,  G06F9/3004 ,  H04L47/52 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9047

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract translation: 交通管理器包括执行单元，其响应于与存储器中的数据排队相关的指令。 指令可以由网络处理器提供，该网络处理器被编程为根据数据生成这样的指令。 这种指令的示例包括（1）不链接到队列的数据单元（固定大小或可变大小）的写入，（2）数据单元相对于彼此的重排序而不移动存储器中的数据单元，以及（ 3）将先前写入的数据单元链接到队列。 网络处理器和流量管理器可以在单个芯片中实现。

公开(公告)号：US5966381A

公开(公告)日：1999-10-12

申请号：US619040

申请日：1996-03-20

Applicant: Clifford James Buckley ,  Israel Cidon ,  Asad Khamisy ,  Raphael Jona Rom

Inventor： Clifford James Buckley ,  Israel Cidon ,  Asad Khamisy ,  Raphael Jona Rom

IPC: H04Q3/00 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC classification number: H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5619 ,  H04L2012/5635 ,  H04L2012/5636

Abstract: An efficient, cost effective method and apparatus for performing resource allocation of available bit rate (ABR) virtual circuit (VC) in an asynchronous transfer mode (ATM) network includes an explicit rate switch process performed at at least one switch of an ABR VC. The process provides a fast and more accurate computation of the number of active VCs in an ATM network. Furthermore, the fair share allocation is calculated at the switch in a way that is efficient and lends itself easily to implementation in hardware. For example, in one embodiment, the fair share is implemented using a series of counters and registers controlled by a state machine. This simple hardware implementation enables fast convergence to a current final state so that timely accurate resource utilization and allocation to the ABR VCs can be determined.

Abstract translation: 用于在异步传输模式（ATM）网络中执行可用比特率（ABR）虚拟电路（VC）的资源分配的有效的，成本有效的方法和装置包括在ABR VC的至少一个交换机上执行的显式速率切换过程。 该过程提供了ATM网络中活动VC数量的快速且更准确的计算。 此外，公平份额分配是以有效的方式在交换机上计算的，并且易于在硬件中实现。 例如，在一个实施例中，公平共享使用由状态机控制的一系列计数器和寄存器来实现。 这种简单的硬件实现能够快速收敛到当前的最终状态，从而可以确定对ABR VC的及时准确的资源利用和分配。

公开(公告)号：US20110265094A1

公开(公告)日：2011-10-27

申请号：US13174560

申请日：2011-06-30

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/383 ,  G06F9/52

Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Abstract translation: 基于一个或多个路径的初始确定，协处理器（提供到存储器的接口）中的逻辑（也称为“同步逻辑”）从多个任务中的每一个接收信号（称为“声明”） （也称为“代码路径”）在任务可能遵循的指令流（例如源自高级软件程序或低级微代码）中。 一旦任务（也被称为“禁用”任务）声明其缺少访问共享数据的需要，同步逻辑允许共享数据被其他指示（也称为“需要”的任务）访问，这些任务已经表明了他们的需要 访问相同。 此外，同步逻辑还允许在当前任务完成对共享数据的访问时由其他有需要的任务访问共享数据（假设当前任务也是有需要的任务）。

公开(公告)号：US20110149989A1

公开(公告)日：2011-06-23

申请号：US13037354

申请日：2011-02-28

Applicant: Andrew Li ,  Michael Lau ,  Asad Khamisy

Inventor： Andrew Li ,  Michael Lau ,  Asad Khamisy

IPC: H04L12/56

CPC classification number: H04L49/9057 ,  G06F9/3004 ,  H04L47/52 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9047

Abstract: A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip.

Abstract translation: 交通管理器包括执行单元，其响应于与存储器中的数据排队相关的指令。 指令可以由网络处理器提供，该网络处理器被编程为根据数据生成这样的指令。 这种指令的示例包括（1）不链接到队列的数据单元（固定大小或可变大小）的写入，（2）数据单元相对于彼此的重排序而不移动存储器中的数据单元，以及（ 3）将先前写入的数据单元链接到队列。 网络处理器和流量管理器可以在单个芯片中实现。

公开(公告)号：US07437535B1

公开(公告)日：2008-10-14

申请号：US10980141

申请日：2004-11-01

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F9/312

CPC classification number: G06F9/3877 ,  G06F9/3004 ,  G06F9/3851

Abstract: This disclosure relates to communications among processors, coprocessors and memory. Specifically, a method and apparatus provide a single-cycle instruction (“store-and-load”) that stores a command to a co-processor to atomically process data and that loads resultant processed data.

Abstract translation: 本公开涉及处理器，协处理器和存储器之间的通信。 具体地说，一种方法和装置提供了一个单周期指令（“存储和加载”），它将协议存储在一个协处理器上以对原始处理数据进行处理并加载结果处理的数据。

公开(公告)号：US5684961A

公开(公告)日：1997-11-04

申请号：US430347

申请日：1995-04-28

Applicant: Israel Cidon ,  Man-Tung Tony Hsiao ,  Raphael Rom ,  Phanindra Jujjavarapu ,  Moshe Sidi ,  Asad Khamisy

Inventor： Israel Cidon ,  Man-Tung Tony Hsiao ,  Raphael Rom ,  Phanindra Jujjavarapu ,  Moshe Sidi ,  Asad Khamisy

IPC: G06F13/00 ,  H04L12/18 ,  H04L12/56 ,  H04Q3/00 ,  H04L12/46

CPC classification number: H04L45/02 ,  H04L12/185 ,  H04L45/10 ,  H04L45/48 ,  H04L49/201 ,  H04L49/25 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5619

Abstract: In a communication network having a set of hosts and switch based label swapping communication nodes, each node has a control processor that is also a host that sends and receives messages via the switching apparatus in its associated node. At least one of the hosts includes a distribution tree set up procedure. That procedure stores source and destination data designating a set of source hosts and a set of destination hosts in the communication network, and defines a distribution tree of virtual connections. The designated source hosts and destination hosts may include the control processors of some or all the network nodes. The defined virtual connections include a virtual connection from each designated source host to all of the designated destination hosts, and message labels for all messages sent by the source hosts to be routed to the destination nodes. The virtual connections convey each message from the source hosts that have the defined message labels to all the designated destination hosts as a single multicast message. The message labels are defined so that overlapping portions of the virtual connections use the same message labels. All the nodes in the distribution tree are programmed by sending one or more virtual connection set up messages that instruct the nodes in the distribution tree on the label swapping data to be stored in each such node.

Abstract translation: 在具有一组主机和基于交换机的标签交换通信节点的通信网络中，每个节点具有控制处理器，该控制处理器也是经由其关联节点中的交换设备发送和接收消息的主机。 至少有一个主机包括分发树设置过程。 该过程存储在通信网络中指定一组源主机和一组目的地主机的源和目的地数据，并且定义虚拟连接的分发树。 指定的源主机和目的主机可以包括一些或所有网络节点的控制处理器。 定义的虚拟连接包括从每个指定的源主机到所有指定的目标主机的虚拟连接，以及由源主机发送到要路由到目标节点的所有消息的消息标签。 虚拟连接将来自具有定义的消息标签的源主机的每个消息作为单个多播消息传送到所有指定的目的地主机。 消息标签被定义为使得虚拟连接的重叠部分使用相同的消息标签。 通过发送一个或多个虚拟连接建立消息来编配分发树中的所有节点，该消息指示分发树中的节点将标签交换数据存储在每个这样的节点中。

公开(公告)号：US20140245315A1

公开(公告)日：2014-08-28

申请号：US13774395

申请日：2013-02-22

Applicant: Alexander Joffe ,  Asad Khamisy

Inventor： Alexander Joffe ,  Asad Khamisy

IPC: G06F9/52

CPC classification number: G06F9/52

Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Abstract translation: 基于一个或多个路径的初始确定，协处理器（提供到存储器的接口）中的逻辑（也称为“同步逻辑”）从多个任务中的每一个接收信号（称为“声明”） （也称为“代码路径”）在任务可能遵循的指令流（例如源自高级软件程序或低级微代码）中。 一旦任务（也被称为“禁用”任务）声明其缺少访问共享数据的需要，同步逻辑允许共享数据被其他指示（也称为“需要”的任务）访问，这些任务已经表明了他们的需要 访问相同。 此外，同步逻辑还允许在当前任务完成对共享数据的访问时由其他有需要的任务访问共享数据（假设当前任务也是有需要的任务）。