公开(公告)号：US06969678B1

公开(公告)日：2005-11-29

申请号：US10700711

申请日：2003-11-03

申请人： Robert J. Chiu ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Errol Todd Ryan

发明人： Robert J. Chiu ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Errol Todd Ryan

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L29/78

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

摘要翻译： 提供一种形成集成电路的方法和集成电路。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。 底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。 底部和顶部硅化物金属形成其硅化物。 介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

公开(公告)号：US07843015B2

公开(公告)日：2010-11-30

申请号：US11229188

申请日：2005-09-15

申请人： Robert J. Chiu ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Errol Todd Ryan

发明人： Robert J. Chiu ,  Paul R. Besser ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Errol Todd Ryan

IPC分类号： H01L21/02

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

摘要翻译： 提供集成电路。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。 底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。 底部和顶部硅化物金属形成其硅化物。 介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

公开(公告)号：US07151020B1

公开(公告)日：2006-12-19

申请号：US10839437

申请日：2004-05-04

申请人： Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Robert J. Chiu ,  Errol Todd Ryan ,  Darin A. Chan ,  Paul R. Besser ,  Paul L. King ,  Minh Van Ngo

发明人： Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Robert J. Chiu ,  Errol Todd Ryan ,  Darin A. Chan ,  Paul R. Besser ,  Paul L. King ,  Minh Van Ngo

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成过渡金属层。 在半导体衬底上形成层间电介质。 然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。