公开(公告)号：US08293606B2

公开(公告)日：2012-10-23

申请号：US12973377

申请日：2010-12-20

申请人： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

发明人： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L22/34

摘要： A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

摘要翻译： 提供了一种身体搭接测试结构及其制造方法。 晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域 所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。 具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

公开(公告)号：US07861195B2

公开(公告)日：2010-12-28

申请号：US12022860

申请日：2008-01-30

申请人： Darin A. Chan ,  Yi Zou ,  Yuansheng Ma ,  Marilyn Wright ,  Mark Michael ,  Donna Michael, legal representative

发明人： Darin A. Chan ,  Yi Zou ,  Yuansheng Ma ,  Marilyn Wright ,  Mark Michael

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/10

摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

摘要翻译： 本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。 然后将该评估信息并入设计规则以提高产量。

公开(公告)号：US07465623B2

公开(公告)日：2008-12-16

申请号：US11467634

申请日：2006-08-28

申请人： Mario M. Pelella ,  Darin A. Chan

发明人： Mario M. Pelella ,  Darin A. Chan

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823878 ,  H01L27/0629

摘要： Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

摘要翻译： 提供了用于在包括在衬底中形成的二极管区域的半导体层/绝缘体/衬底结构上制造SOI部件的方法。 根据一个实施例，该方法包括形成穿过半导体层延伸到绝缘体的浅沟槽隔离（STI）区域。 沉积覆盖STI和半导体层的多晶硅层，并且被图案化以形成至少包括第一掩模区域和第二掩模区域的多晶硅掩模。 使用掩模作为蚀刻掩模，通过STI和绝缘体蚀刻第一和第二开口。 N型和P型离子通过开口注入二极管区域，形成二极管的阳极和阴极。 阳极和阴极通过多晶硅掩模彼此紧密间隔并精确对准。 电触点被制成阳极和阴极。

公开(公告)号：US06764917B1

公开(公告)日：2004-07-20

申请号：US10023350

申请日：2001-12-20

申请人： Darin A. Chan ,  William G. En ,  John G. Pellerin ,  Mark W. Michael

发明人： Darin A. Chan ,  William G. En ,  John G. Pellerin ,  Mark W. Michael

IPC分类号： H01L2176

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

摘要翻译： 制造半导体器件的方法包括在绝缘层上提供硅半导体层，并部分地去除硅层的第一部分。 硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，硅层的第一和第二部分最初可以具有相同的厚度。 还公开了一种半导体器件。

公开(公告)号：US06521510B1

公开(公告)日：2003-02-18

申请号：US10105998

申请日：2002-03-25

申请人： Philip Fisher ,  Darin A. Chan

发明人： Philip Fisher ,  Darin A. Chan

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, including steps of (1) providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; (2) etching through the silicon active layer to form an isolation trench, the isolation trench defining an active island in the silicon active layer, the active island having at least one upper sharp corner; (3) rounding the at least one upper sharp corner of the active island, whereby at least one strained edge portion of the active island is formed; (4) removing at least a part of the at least one strained edge portion; and (5) at least partially filling the isolation trench with a dielectric trench isolation material to form a shallow trench isolation structure. An SOI wafer semiconductor device having a STI isolation structure free from a strained edge portion and a bird's beak.

摘要翻译： 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：（1）提供具有硅有源层，介电绝缘层和硅衬底的绝缘体上硅半导体晶片; （2）蚀刻穿过硅有源层以形成隔离沟槽，隔离沟槽在硅有源层中限定有源岛，活性岛具有至少一个上尖锐角; （3）对活性岛的至少一个上尖锐角进行四舍五入，由此形成活性岛的至少一个应变边缘部分; （4）去除所述至少一个应变边缘部分的至少一部分; 和（5）用绝缘沟槽隔离材料至少部分地填充隔离沟槽以形成浅沟槽隔离结构。 具有没有应变边缘部分和鸟喙的STI隔离结构的SOI晶片半导体器件。

公开(公告)号：US06403492B1

公开(公告)日：2002-06-11

申请号：US09776307

申请日：2001-02-02

申请人： Matthew S. Buynoski ,  Darin A. Chan

发明人： Matthew S. Buynoski ,  Darin A. Chan

IPC分类号： H01L21302

CPC分类号： H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

摘要： A method of trench isolation includes removal of insulation material after planarization of the insulation material and before stripping of a nitride layer such as polish stop layer. The removal of insulation material may be accomplished, for example, by etching. The amount of material removed may be selected so that a surface of the device is substantially planar after one or more subsequent processing steps.

摘要翻译： 沟槽隔离的方法包括在绝缘材料平坦化之后以及剥离诸如抛光停止层之类的氮化物层之前去除绝缘材料。 绝缘材料的去除可以例如通过蚀刻来实现。 可以选择去除的材料的量，使得在一个或多个后续处理步骤之后，该装置的表面基本上是平面的。

公开(公告)号：US07880229B2

公开(公告)日：2011-02-01

申请号：US11874454

申请日：2007-10-18

申请人： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

发明人： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L22/34

摘要： A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

摘要翻译： 提供了一种身体搭接测试结构及其制造方法。 晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域 所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。 具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

公开(公告)号：US20080124884A1

公开(公告)日：2008-05-29

申请号：US11467634

申请日：2006-08-28

申请人： Mario M. Pelella ,  Darin A. Chan

发明人： Mario M. Pelella ,  Darin A. Chan

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823878 ,  H01L27/0629

摘要： Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N— and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.

摘要翻译： 提供了用于在包括在衬底中形成的二极管区域的半导体层/绝缘体/衬底结构上制造SOI部件的方法。 该方法包括根据一个实施例，形成穿过半导体层延伸到绝缘体的浅沟槽隔离（STI）区域。 沉积覆盖STI和半导体层的多晶硅层，并且被图案化以形成至少包括第一掩模区域和第二掩模区域的多晶硅掩模。 使用掩模作为蚀刻掩模，通过STI和绝缘体蚀刻第一和第二开口。 N型和P型离子通过开口注入二极管区域，形成二极管的阳极和阴极。 阳极和阴极通过多晶硅掩模彼此紧密间隔并精确对准。 电触点被制成阳极和阴极。

公开(公告)号：US07250667B2

公开(公告)日：2007-07-31

申请号：US11306663

申请日：2006-01-05

申请人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Paul L. King

发明人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Paul L. King

IPC分类号： H01L29/00

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

摘要翻译： 集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂为具有与硅化物的顶表面分离的类型的可氧化掺杂剂的设定浓度。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 源极/漏极结在半导体衬底中。 硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。 分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。 层间电介质在半导体衬底之上。 触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

公开(公告)号：US07151020B1

公开(公告)日：2006-12-19

申请号：US10839437

申请日：2004-05-04

申请人： Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Robert J. Chiu ,  Errol Todd Ryan ,  Darin A. Chan ,  Paul R. Besser ,  Paul L. King ,  Minh Van Ngo

发明人： Jeffrey P. Patton ,  Austin C. Frenkel ,  Thorsten Kammler ,  Robert J. Chiu ,  Errol Todd Ryan ,  Darin A. Chan ,  Paul R. Besser ,  Paul L. King ,  Minh Van Ngo

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成过渡金属层。 在半导体衬底上形成层间电介质。 然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。