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公开(公告)号：US07843015B2
公开(公告)日：2010-11-30
申请号：US11229188
申请日：2005-09-15
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/02
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译： 提供集成电路。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。 底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。 底部和顶部硅化物金属形成其硅化物。 介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。
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公开(公告)号：US06969678B1
公开(公告)日：2005-11-29
申请号：US10700711
申请日：2003-11-03
申请人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
发明人： Robert J. Chiu , Paul R. Besser , Simon Siu-Sing Chan , Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Errol Todd Ryan
IPC分类号： H01L21/285 , H01L21/336 , H01L21/44 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit, and an integrated circuit, are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.
摘要翻译： 提供一种形成集成电路的方法和集成电路。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。 底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。 底部和顶部硅化物金属形成其硅化物。 介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。
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3.发明授权Conversion of transition metal to silicide through back end processing in integrated circuit technology 有权在集成电路技术中通过后端处理将过渡金属转化为硅化物公开(公告)号：US07151020B1
公开(公告)日：2006-12-19
申请号：US10839437
申请日：2004-05-04
申请人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
发明人： Jeffrey P. Patton , Austin C. Frenkel , Thorsten Kammler , Robert J. Chiu , Errol Todd Ryan , Darin A. Chan , Paul R. Besser , Paul L. King , Minh Van Ngo
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is formed on the source/drain junctions and on the gate. An interlayer dielectric is formed above the semiconductor substrate. Contacts are then formed in the interlayer dielectric, whereby a silicide is formed from the transition metal layer at a temperature no higher than the maximum temperature at which the interlayer dielectric and the contacts are formed.
摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成过渡金属层。 在半导体衬底上形成层间电介质。 然后在层间电介质中形成触点，由此在不高于形成层间电介质和触点的最高温度的温度下由过渡金属层形成硅化物。
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公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。
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公开(公告)号：US07670915B1
公开(公告)日：2010-03-02
申请号：US10791096
申请日：2004-03-01
申请人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
发明人： Errol Todd Ryan , Paul R. Besser , Simon Siu-Sing Chan , Robert J. Chiu , Mehrdad Mahanpour , Minh Van Ngo
IPC分类号： H01L21/20
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.
摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结和栅极上形成硅化物。 在半导体衬底的上方形成有具有接触孔的层间电介质。 接触衬垫形成在接触孔中，然后在接触衬垫上形成接触。 接触衬垫是接触材料的氮化物，并且在低于硅化物的热预算的温度下形成。
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公开(公告)号：US07456062B1
公开(公告)日：2008-11-25
申请号：US11209871
申请日：2005-08-23
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7834 , H01L21/28035 , H01L21/28123 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/66628
摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
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公开(公告)号：US20090032888A1
公开(公告)日：2009-02-05
申请号：US12251959
申请日：2008-10-15
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L21/28035 , H01L21/28123 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/66628
摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
摘要翻译： 侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。 在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。 在清洁处理之后形成外延层。
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8.发明授权Method of eliminating source/drain junction spiking, and device produced thereby 有权消除源极/漏极结尖峰的方法，以及由此产生的器件公开(公告)号：US07132352B1
公开(公告)日：2006-11-07
申请号：US10913184
申请日：2004-08-06
IPC分类号： H01L21/28
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A metallic layer is formed on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are formed immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.
摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底上形成金属层，金属层与半导体衬底反应形成硅化物的早期阶段。 在硅化物的正下方形成植入的浅源极/漏极结。 形成硅化物的最终相。 在半导体衬底上沉积层间电介质，然后与硅化物形成接触。
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公开(公告)号：US08102009B2
公开(公告)日：2012-01-24
申请号：US11538156
申请日：2006-10-03
IPC分类号： H01L29/76
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.
摘要翻译： 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 金属层在半导体衬底上，金属层与半导体衬底反应形成硅化物的早期阶段。 在硅化物的正下方，注入浅的源极/漏极结。 形成硅化物的最终相。 层间电介质在半导体衬底上方，并且与硅化物形成接触。
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公开(公告)号：US07049666B1
公开(公告)日：2006-05-23
申请号：US10859286
申请日：2004-06-01
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is formed over the source/drain junctions. A silicide is formed on the thin insulating layer and on the gate. An interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成一个薄的绝缘层。 在薄绝缘层和栅极上形成硅化物。 在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。
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