公开(公告)号：US08875002B1

公开(公告)日：2014-10-28

申请号：US13535541

申请日：2012-06-28

Applicant: Avijit Dutta

Inventor： Avijit Dutta

IPC: H03M13/13 ,  G06F11/08 ,  H03M13/11 ,  G06F11/10

CPC classification number: H03M13/1148 ,  G06F11/1028 ,  H03M13/19 ,  H03M13/3707 ,  H03M13/3723 ,  H03M13/616

Abstract: A device includes a controller configured to provide a data word and check bits for the data word to decoding logic, the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties:(a) no all 0 columns;(b) all columns are distinct;(c) no linear dependency involving three or less columns;(d) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where j=i+1 and m=k+1; and(e) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where (j=i+1 and m−k=q) or (k=j+1 and m−i=q) or (m=k+1 and j−i=q) for all integer values of q such that q>1 and q =2 and d

Abstract translation: 一种设备包括：控制器，被配置为向解码逻辑提供数据字和数据字的校验位，所述解码逻辑被配置为产生数据字的解码，以及根据具有所述数据字的H矩阵的数据字的校验位 以下属性：（a）不全0列; （b）所有栏目是不同的; （c）不包括三个或更少列的线性依赖; （d）不涉及列Ci，Cj，Ck，Cm，其中m> k> j> i的线性依赖性，其中j = i + 1和m = k + 1; 其中（j = i + 1和m-k = q）或（k = j + 1和m-1），并且（e）不涉及列Ci，Cj，Ck，Cm， 对于q的所有整数值，i = q）或（m = k + 1和j-i = q），使得q> 1和q <= d，其中d> = 2和d <= n-1其中n- k是一些校验位。

公开(公告)号：US20130290795A1

公开(公告)日：2013-10-31

申请号：US13980287

申请日：2012-01-17

Applicant: Janusz Rajski ,  Mark A. Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jakub Janicki ,  Jerzy Tyszer ,  Avijit Dutta

Inventor： Janusz Rajski ,  Mark A. Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jakub Janicki ,  Jerzy Tyszer ,  Avijit Dutta

IPC: H04L12/26

CPC classification number: H04L43/50 ,  G01R31/318335 ,  G06F11/263

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.

Abstract translation: 公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。 编码测试数据以导出需要少量核心输入通道的压缩测试模式。 相应地确定每个压缩测试图案的核心输入/输出通道要求信息。 压缩的模式被分组成测试模式类。 测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。 可以独立于测试数据设计测试访问机制。

公开(公告)号：US20110258504A1

公开(公告)日：2011-10-20

申请号：US13091092

申请日：2011-04-20

Applicant: Wu-Tung Cheng ,  Manish Sharma ,  Avijit Dutta ,  Robert Brady Benware ,  Mark A. Kassab

Inventor： Wu-Tung Cheng ,  Manish Sharma ,  Avijit Dutta ,  Robert Brady Benware ,  Mark A. Kassab

IPC: G06F11/00

CPC classification number: G01R31/3177 ,  G01R31/318563 ,  G06F11/2242

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.

Abstract translation: 公开了用于基于分区的测试访问机制（TAM）的方法，装置和系统的代表性实施例。 测试响应数据由被测电路中的多个扫描链的扫描单元捕获，并与预期的良好CUT的测试响应数据进行比较以产生检查值。 基于检查值，分区通过/失败信号由分区方案生成器生成。 每个分区方案生成器被配置为为分区方案之一生成分区通过/失败信号之一。 分区方案将扫描单元划分为一组非重叠分区。 基于分区通过/失败信号，可以执行故障诊断处理。

公开(公告)号：US08607107B2

公开(公告)日：2013-12-10

申请号：US13091092

申请日：2011-04-20

Applicant: Wu-Tung Cheng ,  Manish Sharma ,  Avijit Dutta ,  Robert Brady Benware ,  Mark A Kassab

Inventor： Wu-Tung Cheng ,  Manish Sharma ,  Avijit Dutta ,  Robert Brady Benware ,  Mark A Kassab

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/318563 ,  G06F11/2242

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.

Abstract translation: 公开了用于基于分区的测试访问机制（TAM）的方法，装置和系统的代表性实施例。 测试响应数据由被测电路中的多个扫描链的扫描单元捕获，并与预期的良好CUT的测试响应数据进行比较以产生检查值。 基于检查值，分区通过/失败信号由分区方案生成器生成。 每个分区方案生成器被配置为为分区方案之一生成分区通过/失败信号之一。 分区方案将扫描单元划分为一组非重叠分区。 基于分区通过/失败信号，可以执行故障诊断处理。

公开(公告)号：US09088522B2

公开(公告)日：2015-07-21

申请号：US13980287

申请日：2012-01-17

Applicant: Janusz Rajski ,  Mark A Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jakub Janicki ,  Jerzy Tyszer ,  Avijit Dutta

Inventor： Janusz Rajski ,  Mark A Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Jakub Janicki ,  Jerzy Tyszer ,  Avijit Dutta

IPC: H04L12/26 ,  G01R31/3183 ,  G06F11/263

CPC classification number: H04L43/50 ,  G01R31/318335 ,  G06F11/263

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.

Abstract translation: 公开了用于在电路系统中测试多个核的测试调度的方法，装置和系统的代表性实施例。 编码测试数据以导出需要少量核心输入通道的压缩测试模式。 相应地确定每个压缩测试图案的核心输入/输出通道要求信息。 压缩的模式被分组成测试模式类。 测试模式类的形成之后是分配电路输入和输出通道以及测试应用时隙，其可以包括将互补测试模式类合并成可以与特定测试访问机制一起工作的集群。 可以独立于测试数据设计测试访问机制。