公开(公告)号：US07649409B1

公开(公告)日：2010-01-19

申请号：US11877255

申请日：2007-10-23

申请人： Yongseon Koh ,  Babak Matinpour ,  Vijaya Ceekala ,  Ramsin Ziazadeh

发明人： Yongseon Koh ,  Babak Matinpour ,  Vijaya Ceekala ,  Ramsin Ziazadeh

IPC分类号： H03B1/00

CPC分类号： H04B3/14 ,  H03F3/45085 ,  H03F3/45475

摘要： An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.

摘要翻译： 集成电路包括被耦合以从集成电路外部接收信号的引脚和输入网络。 输入网络通过衰减低频输入信号来均衡输入信号，而不是在引脚处接收的高频输入信号。 输入网络被配置为响应于AC耦合输入信号或在具有宽共模范围的引脚处接收的DC耦合输入信号，在输入网络的输出处产生DC偏置电压。

公开(公告)号：US07994807B1

公开(公告)日：2011-08-09

申请号：US11877519

申请日：2007-10-23

申请人： Yongseon Koh ,  Babak Matinpour ,  Vijaya Ceekala

发明人： Yongseon Koh ,  Babak Matinpour ,  Vijaya Ceekala

IPC分类号： G01R31/3187

CPC分类号： G01R31/2884

摘要： An analog device under test circuit and a built-in test circuit for testing an AC transfer characteristic of the analog device under test are fabricated on an integrated circuit. The built-in test circuit includes an amplitude detector that detects the amplitude of the output signal of the analog device under test. The test time is reduced by sampling in real-time the DC value corresponding to the amplitude of the analog device under test. An additional reduction in the test time is achieved by using comparators with upper and lower limit reference signals and a pass-fail logic test.

摘要翻译： 一个模拟器件被测电路和一个用于测试被测模拟器件的交流传输特性的内置测试电路是在集成电路上制造的。 内置测试电路包括检测被测模拟器件的输出信号振幅的振幅检测器。 通过实时采样对应于被测模拟装置的幅度的DC值，可以减少测试时间。 通过使用具有上限和下限参考信号的比较器和通过失效逻辑测试来实现测试时间的进一步减少。