公开(公告)号：US07856512B2

公开(公告)日：2010-12-21

申请号：US11213229

申请日：2005-08-26

申请人： Stephen Charles Hilla ,  Barry Scott Burns ,  Timothy Marsteiner

发明人： Stephen Charles Hilla ,  Barry Scott Burns ,  Timothy Marsteiner

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： H04L47/10 ,  H04L41/0893 ,  H04L43/00 ,  H04L43/06 ,  H04L43/0817 ,  H04L43/10

摘要： The invention comprises system and method for offloading a processor tasked with calendar processing of channel status information. The method comprises multiplexing channel status information received from a plurality of physical interfaces; grouping the channels based on bandwidth; comparing current and previous status information of a group of channels in a first memory; sending current channel status to the processor only if the status of any of the channels in the group has changed; and periodically synchronizing channel status information in the first memory to status information in the processor's memory. The system comprises: multiplexer to combine channel status information received from the interfaces and means for grouping, based on bandwidth, the channels; hardware assist engine to send current channel status to the processor only if channel status has changed; and device to synchronize channel status information in the hardware assist engine to status information in the processor's memory.

摘要翻译： 本发明包括用于卸载任务处理信道状态信息的日历处理的处理器的系统和方法。 该方法包括：复用从多个物理接口接收的信道状态信息; 基于带宽对信道进行分组; 比较第一存储器中的一组信道的当前状态信息和先前状态信息; 只有当组中任何通道的状态发生变化时才将当前通道状态发送到处理器; 并且将第一存储器中的通道状态信息周期性地同步到处理器存储器中的状态信息。 该系统包括：多路复用器，用于组合从接口接收到的信道状态信息，以及用于基于带宽对信道进行分组的装置; 硬件辅助引擎仅当通道状态发生变化时才将当前通道状态发送到处理器; 以及将硬件辅助引擎中的通道状态信息同步到处理器存储器中的状态信息的设备。

公开(公告)号：US08112584B1

公开(公告)日：2012-02-07

申请号：US10878891

申请日：2004-06-28

申请人： John J. Williams, Jr. ,  John Andrew Fingerhut ,  Man Kit Tang ,  Barry Scott Burns

发明人： John J. Williams, Jr. ,  John Andrew Fingerhut ,  Man Kit Tang ,  Barry Scott Burns

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/0802 ,  G06F12/0866 ,  G06F12/0888 ,  G06F2212/1021

摘要： Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for a storage controller (e.g., memory controller, disk controller, etc.) performing a set of multiple operations on cached data with a no-miss guarantee until the multiple operations are complete, which may, for example, be used by a packet processor to quickly update multiple statistics values (e.g., byte, packet, error counts, etc.) based on processed packets. Operations to be performed on data at the same address and/or in a common data structure are grouped together and burst so that they arrive at the storage system in contiguous succession for the storage controller to perform. By not allowing the storage controller to flush the data from its cache until all of the operations are performed, even a tiny cache attached to the storage controller can reduce the bandwidth and latency of updating the data.

摘要翻译： 公开了尤其是对具有no的缓存数据执行一组多个操作的存储控制器（例如，存储器控制器，磁盘控制器等）的方法，装置，数据结构，计算机可读介质，机制和装置 - 直到多个操作完成为止，这可以例如被分组处理器用于基于处理的分组快速更新多个统计值（例如，字节，分组，错误计数等）。 对相同地址和/或公共数据结构中的数据执行的操作被分组在一起并突发，使得它们以连续的顺序到达存储系统以使存储控制器执行。 通过不允许存储控制器从其高速缓存中刷新数据，直到执行所有操作，即使连接到存储控制器的小型缓存也可以减少更新数据的带宽和延迟。

公开(公告)号：US20090271570A1

公开(公告)日：2009-10-29

申请号：US12111436

申请日：2008-04-29

申请人： Barry Scott BURNS ,  Chirag SHROFF

发明人： Barry Scott BURNS ,  Chirag SHROFF

IPC分类号： G06F12/00

CPC分类号： G06F11/1064

摘要： Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with content-addressable memory lookup operations with error detection. Lookup operations are performed on two identical sets of content-addressable memory entries to identify two lookup results. An error detection operation is performed on the highest-priority matching entry of each set of content-addressable memory entries. An overall lookup result is determined based on the lookup and error detection results.

摘要翻译： 公开了尤其涉及与具有错误检测的内容可寻址存储器查找操作相关联的方法，装置，计算机存储介质，机制和装置。 在两组相同的内容可寻址内存条目上执行查找操作，以识别两个查找结果。 对每组可内容寻址的存储器条目的最高优先级匹配条目执行错误检测操作。 基于查找和错误检测结果确定总体查找结果。