Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods
    1.
    发明授权
    Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods 有权
    用于制造磁性细胞结的方法和产生和/或用于这种方法的结构

    公开(公告)号:US07205164B1

    公开(公告)日:2007-04-17

    申请号:US11039301

    申请日:2005-01-19

    IPC分类号: H01L21/00

    摘要: Methods for patterning a magnetic cell junction and a topography used for and/or resulting from such methods are provided. In particular, a method is provided which includes etching portions of a topography adjacent to a patterned photoresist layer to a level within a cap film of the topography, removing etch residues from the topography and subsequently etching the remaining portions of the cap film to expose an uppermost magnetic layer. Another method is provided which includes patterning a dielectric mask layer above a patterned upper portion of a magnetic cell junction and ion milling a lower portion of the magnetic cell junction in alignment with the mask layer. An exemplary topography which may result and/or may be used for such methods includes a stack of layers having a dual layer cap film arranged above at least two magnetic layers spaced apart by a tunneling layer.

    摘要翻译: 提供了用于图案化磁性细胞结的方法和用于和/或由这些方法产生的形貌。 特别地,提供了一种方法,其包括将与图案化的光致抗蚀剂层相邻的形貌的部分蚀刻到地形的盖膜内的水平,从形貌去除蚀刻残留物,随后蚀刻盖膜的剩余部分以暴露 最上层的磁性层。 提供了另一种方法,其包括将介电掩模层图案化在磁性细胞结的图案化的上部上方,并离子铣削与掩模层对准的磁性细胞结的下部。 可能导致和/或可用于这种方法的示例性形貌包括具有布置在至少两个由隧道层间隔开的磁性层之上的双层帽膜的层叠。

    Magnetic tunneling junction configuration and a method for making the same
    2.
    发明授权
    Magnetic tunneling junction configuration and a method for making the same 失效
    磁隧道结结构及其制作方法

    公开(公告)号:US06897532B1

    公开(公告)日:2005-05-24

    申请号:US10122733

    申请日:2002-04-15

    摘要: A method for forming a magnetic tunneling junction (MJT) is provided. In some embodiments, the method may include patterning one or more magnetic layers to form an upper portion of a MTJ. The method may further include patterning one or more additional layers to form a lower portion of the MTJ. In some cases, the lower portion may include a tunneling layer of the MTJ having a width greater than the upper portion. In addition, in some embodiments the method may further include patterning an electrode below the lower portion. In some cases, the electrode may include a lowermost layer with a thickness equal to or less than approximately 100 angstroms. In addition or alternatively, the electrode may have a width greater than the width of the tunneling layer. In yet other embodiments, the method may include forming spacers along the sidewalls of the upper and/or lower portions.

    摘要翻译: 提供一种用于形成磁隧道结(MJT)的方法。 在一些实施例中,该方法可以包括图案化一个或多个磁性层以形成MTJ的上部。 该方法还可以包括图案化一个或多个附加层以形成MTJ的下部。 在一些情况下,下部可以包括具有大于上部的宽度的MTJ的隧道层。 此外,在一些实施例中,该方法还可以包括在下部部分下方图案化电极。 在一些情况下,电极可以包括厚度等于或小于约100埃的最下层。 另外或替代地,电极可以具有大于隧道层宽度的宽度。 在其它实施例中,该方法可以包括沿着上部和/或下部的侧壁形成间隔物。

    Reducing defect formation within an etched semiconductor topography
    3.
    发明授权
    Reducing defect formation within an etched semiconductor topography 有权
    减少蚀刻半导体形貌内的缺陷形成

    公开(公告)号:US07129178B1

    公开(公告)日:2006-10-31

    申请号:US10074888

    申请日:2002-02-13

    IPC分类号: H01L21/302 H01L21/461

    摘要: A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

    摘要翻译: 提供了一种方法,其包括在蚀刻室中蚀刻一个或多个层,同时将比氦更重的惰性气体引入蚀刻室。 在优选实施例中,引入这种惰性气体可以减少半导体形貌的蚀刻部分内的缺陷的形成。 这样的缺陷可以包括例如氮化物的双层堆积物和包含硅的材料。 在一些实施例中,该方法可以包括在单个蚀刻室内蚀刻一层层。 层叠层可以包括例如介于抗反射层和下层之间的氮化物层。 此外,单蚀刻室可以是设计用于蚀刻包含硅的材料的等离子体蚀刻室。 因此,该方法可以包括在设计成蚀刻包含硅的材料的等离子体蚀刻室中蚀刻抗反射层。

    MRAM field-inducing layer configuration
    4.
    发明授权
    MRAM field-inducing layer configuration 失效
    MRAM场诱导层配置

    公开(公告)号:US06891193B1

    公开(公告)日:2005-05-10

    申请号:US10184673

    申请日:2002-06-28

    IPC分类号: H01L27/14 H01L27/22

    CPC分类号: H01L27/222

    摘要: A magnetic random access memory (MRAM) device is provided which includes a conductive line configured to induce a magnetic field with a higher magnitude along at least a portion of a magnetic cell junction than along a spacing arranged adjacent to the magnetic cell junction. In some embodiments, the conductive line may include first portions aligned with a plurality of magnetic cell junctions and second portions aligned with spacings arranged between the plurality of magnetic cell junctions. In such an embodiment, the first portions preferably include different peripheral profiles than the second portions. A method for fabricating such an MRAM device is also provided herein. The method may include aligning magnetic cell junctions and first portions of a field-inducing line with each other such that at least part of the first portions of the field-inducing line are configured to conduct a higher density of current than second portions of the field-inducing line.

    摘要翻译: 提供一种磁性随机存取存储器(MRAM)器件,其包括导线,其被配置成沿着沿与磁性细胞结邻近的间隔沿磁性细胞结的至少一部分感应具有较大幅度的磁场。 在一些实施例中,导电线可以包括与多个磁性细胞结连接的第一部分和与布置在多个磁性细胞结之间的间隔对准的第二部分。 在这样的实施例中,第一部分优选地包括与第二部分不同的外围轮廓。 本文还提供了一种用于制造这种MRAM器件的方法。 该方法可以包括将磁场连接和场致感线的第一部分彼此对准,使得场致感线的第一部分的至少一部分被配置为传导比场的第二部分更高的电流密度 诱导线。

    Metal etch process selective to metallic insulating materials
    5.
    发明授权
    Metal etch process selective to metallic insulating materials 失效
    金属蚀刻工艺对金属绝缘材料有选择性

    公开(公告)号:US06972265B1

    公开(公告)日:2005-12-06

    申请号:US10122737

    申请日:2002-04-15

    摘要: A method is provided which includes patterning one or more metal layers arranged above a metal insulating layer and terminating the patterning process upon exposure of the metal insulating layer. In particular, the method may be adapted to be more selective to the metal insulating layer than the one or more metal layers. In general, such an adaptation may include exposing the semiconductor topography to an etch chemistry comprising hydrogen bromide. In some cases, the etch chemistry may further include a fluorinated hydrocarbon. In yet other embodiments, the method may further or alternatively include using a reactive ion etch process, etching at a relatively low temperature, using a resist mask, and/or using an etch chemistry substantially absent of an oxygen plasma. In this manner, the method may, in some embodiments, include patterning the one or more metal layers using a reactive ion etch process substantially absent of an oxygen plasma.

    摘要翻译: 提供一种方法,其包括图案化布置在金属绝缘层上方的一个或多个金属层,并且在暴露金属绝缘层时终止图案化工艺。 特别地,该方法可以适于比一个或多个金属层对金属绝缘层更有选择性。 通常,这种适应可以包括将半导体形貌暴露于含有溴化氢的蚀刻化学品。 在一些情况下,蚀刻化学可以进一步包括氟化烃。 在其它实施例中,该方法可以进一步或可选地包括使用反应离子蚀刻工艺,使用抗蚀剂掩模在相对低的温度下进行蚀刻,和/或使用基本上不含氧等离子体的蚀刻化学。 以这种方式,在一些实施例中,该方法可以包括使用基本上不含氧等离子体的反应离子蚀刻工艺图案化一个或多个金属层。