公开(公告)号：US06833622B1

公开(公告)日：2004-12-21

申请号：US10375534

申请日：2003-02-27

申请人： Andrey V. Zagrebelny ,  Daniel J. Arnzen ,  Yitzhak Gilboa

发明人： Andrey V. Zagrebelny ,  Daniel J. Arnzen ,  Yitzhak Gilboa

IPC分类号： H01L2348

CPC分类号： H01L21/76819 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/76237 ,  Y10S438/926 ,  Y10S438/975

摘要： A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.

摘要翻译： 提供了一种用于在半导体形貌的非活性区域内制造基本平坦表面的虚拟结构图案。 特别地，提供了半导体形貌，其包括非活性区域，其包括牺牲环形虚设结构，该牺牲环形虚设结构构造成围绕布置在半导体形貌的有源区域内的器件的最小临界尺寸的平方以上。 在优选实施例中，该区域专门用于在半导体拓扑的半导体衬底内形成隔离结构。 因此，提供半导体形貌，其包括布置在邻接隔离结构的间隔内的单独的隔离结构，其以半导体衬底的一部分内的栅格图案布置。 此外，提供一种半导体器件，其包括具有多个相似尺寸且均匀排列的环形扩散区域的非活性区域。

公开(公告)号：US07129178B1

公开(公告)日：2006-10-31

申请号：US10074888

申请日：2002-02-13

申请人： Benjamin C. E. Schwarz ,  Chan Lon Yan ,  Hanna Bamnolker ,  Daniel J. Arnzen

发明人： Benjamin C. E. Schwarz ,  Chan Lon Yan ,  Hanna Bamnolker ,  Daniel J. Arnzen

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137

摘要： A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

摘要翻译： 提供了一种方法，其包括在蚀刻室中蚀刻一个或多个层，同时将比氦更重的惰性气体引入蚀刻室。 在优选实施例中，引入这种惰性气体可以减少半导体形貌的蚀刻部分内的缺陷的形成。 这样的缺陷可以包括例如氮化物的双层堆积物和包含硅的材料。 在一些实施例中，该方法可以包括在单个蚀刻室内蚀刻一层层。 层叠层可以包括例如介于抗反射层和下层之间的氮化物层。 此外，单蚀刻室可以是设计用于蚀刻包含硅的材料的等离子体蚀刻室。 因此，该方法可以包括在设计成蚀刻包含硅的材料的等离子体蚀刻室中蚀刻抗反射层。