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    Reducing defect formation within an etched semiconductor topography
    2.
    发明授权
    Reducing defect formation within an etched semiconductor topography 有权
    减少蚀刻半导体形貌内的缺陷形成

    公开(公告)号：US07129178B1

    公开(公告)日：2006-10-31

    申请号：US10074888

    申请日：2002-02-13

    申请人： Benjamin C. E. Schwarz ,  Chan Lon Yan ,  Hanna Bamnolker ,  Daniel J. Arnzen

    发明人： Benjamin C. E. Schwarz ,  Chan Lon Yan ,  Hanna Bamnolker ,  Daniel J. Arnzen

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137

    摘要： A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

    摘要翻译： 提供了一种方法，其包括在蚀刻室中蚀刻一个或多个层，同时将比氦更重的惰性气体引入蚀刻室。 在优选实施例中，引入这种惰性气体可以减少半导体形貌的蚀刻部分内的缺陷的形成。 这样的缺陷可以包括例如氮化物的双层堆积物和包含硅的材料。 在一些实施例中，该方法可以包括在单个蚀刻室内蚀刻一层层。 层叠层可以包括例如介于抗反射层和下层之间的氮化物层。 此外，单蚀刻室可以是设计用于蚀刻包含硅的材料的等离子体蚀刻室。 因此，该方法可以包括在设计成蚀刻包含硅的材料的等离子体蚀刻室中蚀刻抗反射层。

    Method for controlling the oxidation of implanted silicon
    3.
    发明授权
    Method for controlling the oxidation of implanted silicon 失效
    控制植入硅氧化的方法

    公开(公告)号：US06555484B1

    公开(公告)日：2003-04-29

    申请号：US08878728

    申请日：1997-06-19

    申请人： Krishnaswamy Ramkumar ,  Hanna Bamnolker

    发明人： Krishnaswamy Ramkumar ,  Hanna Bamnolker

    IPC分类号： H01L21265

    CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/2822 ,  Y10S438/911 ,  Y10S438/92 ,  Y10S438/981

    摘要： Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.

    摘要翻译： 用掺杂剂/离子注入半导体衬底的两个不同区域。 注入可以通过设置在衬底上的牺牲氧化层发生。 在一个或两个区域中植入之后，可以对衬底进行退火并去除牺牲氧化物层。 然后在衬底的注入区域上生长氧化物层。 对于一些实施例，衬底可以用砷和/或磷进行注入。 此外，退火可以在约900℃至950℃的温度下进行约30至120分钟。

    Method for and structure formed from fabricating a relatively deep isolation structure
    5.
    发明授权
    Method for and structure formed from fabricating a relatively deep isolation structure 有权
    通过制造相对较深的隔离结构形成的方法和结构

    公开(公告)号：US06794269B1

    公开(公告)日：2004-09-21

    申请号：US10324989

    申请日：2002-12-20

    申请人： Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

    发明人： Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

    IPC分类号： H01L2176

    CPC分类号： H01L21/763 ,  H01L21/76202

    摘要： A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

    摘要翻译： 提供了一种方法，其包括在半导体形貌内形成深度隔离结构。 在一些情况下，该方法可以包括在半导体层内形成第一隔离结构并蚀刻隔离结构内的开口以暴露半导体层。 此外，该方法可以包括蚀刻半导体层以形成延伸穿过隔离结构和半导体层的至少一部分的沟槽。 在一些情况下，该方法可以包括去除沉积在沟槽内的第一填充层的部分，使得填充层的上表面在沟槽的上部下方。 在这样的实施例中，沟槽的空缺部分可以填充第二填充层。 在其他实施例中，该方法可以包括平坦化沟槽内的第一填充层，随后氧化填充层的上部。

    Method of forming contact openings
    6.
    发明授权
    Method of forming contact openings 有权
    形成接触孔的方法

    公开(公告)号：US06756315B1

    公开(公告)日：2004-06-29

    申请号：US09672836

    申请日：2000-09-29

    申请人： Hanna Bamnolker ,  Prashant Phatak ,  Usha Raghuram ,  Sam Geha

    发明人： Hanna Bamnolker ,  Prashant Phatak ,  Usha Raghuram ,  Sam Geha

    IPC分类号： H01L21302

    CPC分类号： H01L21/02063 ,  H01L21/76802 ,  H01L21/76814

    摘要： The present invention provides a method of forming, in semiconductor substrates, contact openings having low contact resistance. The method involves, in particular, the introduction of a “soft etch” cleaning step that is used to clean the bottom of the contact openings. The “soft etch” cleaning step uses fluorocarbon chemistry. It is shown that the resulting resistance of the contact openings is reduced.

    摘要翻译： 本发明提供了一种在半导体衬底中形成具有低接触电阻的接触开口的方法。 该方法特别涉及引入用于清洁接触开口底部的“软蚀刻”清洁步骤。 “软蚀刻”清洁步骤使用碳氟化合物。 显示出所产生的接触开口的电阻降低。