公开(公告)号：US06214722B1

公开(公告)日：2001-04-10

申请号：US09286005

申请日：1999-04-05

申请人： Chien-Chih Lin ,  Bill Hsu ,  Nien-Tsu Peng

发明人： Chien-Chih Lin ,  Bill Hsu ,  Nien-Tsu Peng

IPC分类号： H01L214763

CPC分类号： H01L23/53295 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing an interconnect on a wafer having an edge region and an interior region comprises the steps of: forming an insulating layer on the wafer having an interior region and an edge region; forming an opening penetrating through the insulating layer in the interior region and removing a portion of the insulating layer to expose a surface of the wafer in the edge region, simultaneously; forming a conductive layer over the insulating layer and the exposed surface of the wafer and filling the opening; and patterning the conductive layer to form a wire in the opening.

摘要翻译： 在具有边缘区域和内部区域的晶片上制造互连的方法包括以下步骤：在具有内部区域和边缘区域的晶片上形成绝缘层; 形成穿过所述内部区域中的所述绝缘层的开口，并同时去除所述绝缘层的一部分以暴露所述边缘区域中的所述晶片的表面; 在所述绝缘层和所述晶片的暴露表面上形成导电层并填充所述开口; 以及图案化所述导电层以在所述开口中形成导线。

公开(公告)号：US5994225A

公开(公告)日：1999-11-30

申请号：US733476

申请日：1996-10-18

申请人： Ming-Tsung Liu ,  Tsung-Yuan Hung ,  Bill Hsu

发明人： Ming-Tsung Liu ,  Tsung-Yuan Hung ,  Bill Hsu

IPC分类号： G03F7/40 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/302

CPC分类号： H01L21/0274 ,  G03F7/40 ,  H01L21/32136 ,  Y10S438/976

摘要： A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

摘要翻译： 一种用于蚀刻金属的方法，其可以增加旨在相对于覆盖金属层的光致抗蚀剂层被蚀刻的金属层的金属对光致抗蚀剂蚀刻选择性。 该方法包括在金属层上形成帽氧化物层的第一步骤; 在所述盖氧化物层上形成具有所需图案的光致抗蚀剂层的第二步骤; 在光致抗蚀剂层上进行离子注入工艺的第三步骤; 以及通过使用光致抗蚀剂层作为掩模在半导体晶片上进行蚀刻处理以蚀刻远离未被光致抗蚀剂层覆盖的金属层的暴露部分的最后步骤。 通过实验发现，与现有技术相比，本发明提供了显着改进的蚀刻选择性。

公开(公告)号：US5514623A

公开(公告)日：1996-05-07

申请号：US387435

申请日：1995-02-13

申请人： Joe Ko ,  Bill Hsu

发明人： Joe Ko ,  Bill Hsu

IPC分类号： H01L23/485 ,  H01L21/283 ,  H01L21/3065

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05599 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S438/91

摘要： A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a polysilicon layer is formed on the substrate to act as a first contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forms large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, by direct contact to the first metal at the large contact pad area, and through the openings in the second insulator to the first metal interconnection. Finally, a passivation layer is formed over the second metal layer.

摘要翻译： 在硅衬底中形成用于集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 在衬底上形成多晶硅层的图案层，以作为集成电路的第一接触。 在多晶硅层上形成绝缘层，通过绝缘层形成到多晶硅层的开口。 在绝缘体上形成第一金属层，使得金属通过开口与多晶硅电连接，并且还形成大的接触焊盘区域。 第一金属被图案化以在大接触焊盘区域和集成电路之间形成电断路。 这种断开可防止在等离子体环境中的后续处理期间由于电荷积聚而对集成电路的电气损坏。 第二绝缘层被形成并图案化以提供到第一金属层的通孔的开口。 第二层金属形成在大的接触焊盘区域上并且在电断裂之上，使得第二金属通过在大的接触焊盘区域处直接接触第一金属并且通过在第二金属的开口处电连接到第一金属 第二绝缘体到第一金属互连。 最后，在第二金属层上形成钝化层。

公开(公告)号：US5393701A

公开(公告)日：1995-02-28

申请号：US44931

申请日：1993-04-08

申请人： Joe Ko ,  Bill Hsu

发明人： Joe Ko ,  Bill Hsu

IPC分类号： H01L23/485 ,  H01L21/443

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05599 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  Y10S438/91

摘要： A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a conductive polysilicon is formed on the substrate to act as a first conductive contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forming large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, via direct contact to the first metal at the large contact pad area, and through the openings in the second insulator to the first metal interconnection. Finally, a passivation layer is formed over the second metal layer.

摘要翻译： 在硅衬底中形成用于集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 导电多晶硅的图案层形成在衬底上以用作集成电路的第一导电接触。 在多晶硅层上形成绝缘层，通过绝缘层形成到多晶硅层的开口。 在绝缘体上形成第一金属层，使得金属通过开口电连接到多晶硅，并且还形成大的接触焊盘区域。 第一金属被图案化以在大接触焊盘区域和集成电路之间形成电断路。 这种断开可防止在等离子体环境中的后续处理期间由于电荷积聚而对集成电路的电气损坏。 第二绝缘层被形成并图案化以提供到第一金属层的通孔的开口。 第二层金属形成在大的接触焊盘区域上并且在电断裂之上，使得第二金属通过与大接触焊盘区域处的第一金属直接接触而电连接到第一金属，并通过 第二绝缘体到第一金属互连。 最后，在第二金属层上形成钝化层。

公开(公告)号：USD479376S1

公开(公告)日：2003-09-02

申请号：US29175368

申请日：2003-02-05

申请人： Bill Hsu

设计人： Bill Hsu