公开(公告)号：US06380073B1

公开(公告)日：2002-04-30

申请号：US09650910

申请日：2000-08-29

申请人： Tsing-Fong Hwang ,  Tsung-Yuan Hung

发明人： Tsing-Fong Hwang ,  Tsung-Yuan Hung

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L2221/1026 ,  H01L2221/1063

摘要： A method for forming metal interconnection structure is disclosed. A semiconductor substrate is provided, the substrate has a first silicon nitride layer formed thereon, and a first inter-metal layer formed on the surface of the first stop layer. The first inter-metal layer is etched to form an opening in the inter-metal layer using the first photoresist. A second silicon nitride layer is formed. A dielectric layer is formed. A second inter-metal layer is formed. The second inter-metal layer is etched using the second photoresist. The third silicon nitride layer is formed. The third layer is etched back. The dielectric layer is removed. The third stop layer, the second silicon, nitride layer and the first stop layer are etched. The barrier layer is deposited into a via trench. The trenches are filled by a metal layer. Finally, the metal layer is planarized.

摘要翻译： 公开了一种用于形成金属互连结构的方法。 提供了半导体衬底，所述衬底具有形成在其上的第一氮化硅层和形成在所述第一停止层的表面上的第一金属间层。 使用第一光致抗蚀剂蚀刻第一金属间层以在金属间层中形成开口。 形成第二氮化硅层。 形成介电层。 形成第二金属间层。 使用第二光致抗蚀剂蚀刻第二金属间层。 形成第三氮化硅层。 第三层被回蚀。 去除电介质层。 蚀刻第三阻挡层，第二硅，氮化物层和第一阻挡层。 阻挡层被沉积到通孔中。 沟槽由金属层填充。 最后，将金属层平坦化。

公开(公告)号：US5994225A

公开(公告)日：1999-11-30

申请号：US733476

申请日：1996-10-18

申请人： Ming-Tsung Liu ,  Tsung-Yuan Hung ,  Bill Hsu

发明人： Ming-Tsung Liu ,  Tsung-Yuan Hung ,  Bill Hsu

IPC分类号： G03F7/40 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/302

CPC分类号： H01L21/0274 ,  G03F7/40 ,  H01L21/32136 ,  Y10S438/976

摘要： A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

摘要翻译： 一种用于蚀刻金属的方法，其可以增加旨在相对于覆盖金属层的光致抗蚀剂层被蚀刻的金属层的金属对光致抗蚀剂蚀刻选择性。 该方法包括在金属层上形成帽氧化物层的第一步骤; 在所述盖氧化物层上形成具有所需图案的光致抗蚀剂层的第二步骤; 在光致抗蚀剂层上进行离子注入工艺的第三步骤; 以及通过使用光致抗蚀剂层作为掩模在半导体晶片上进行蚀刻处理以蚀刻远离未被光致抗蚀剂层覆盖的金属层的暴露部分的最后步骤。 通过实验发现，与现有技术相比，本发明提供了显着改进的蚀刻选择性。

公开(公告)号：US06211048B1

公开(公告)日：2001-04-03

申请号：US09241792

申请日：1999-02-01

申请人： Tsing-Fong Hwang ,  Tsung-Yuan Hung

发明人： Tsing-Fong Hwang ,  Tsung-Yuan Hung

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L29/66545

摘要： A method for reducing salicide lateral growth. A substrate having a gate structure and an anti-reflection layer on the gate structure is provided. A spacer is formed on the side wall of the gate structure and the anti-reflection layer. Then, the anti-reflection layer is removed to expose the gate structure; wherein the gate structure and the spacers together form a recess structure. A salicide layer is formed on the gate structure in the recess structure and on the substrate.

摘要翻译： 一种减少自杀性侧生长的方法。 提供了一种在栅极结构上具有栅极结构和抗反射层的衬底。 在栅极结构和防反射层的侧壁上形成间隔物。 然后，去除防反射层以露出栅极结构; 其中所述栅极结构和所述间隔物一起形成凹陷结构。 在凹槽结构和衬底上的栅极结构上形成自对准硅层。

公开(公告)号：US06100183A

公开(公告)日：2000-08-08

申请号：US132384

申请日：1998-08-11

申请人： William Lu ,  Tsung-Yuan Hung ,  Chi-Cheng Yang ,  Ching-Hsing Hsieh

发明人： William Lu ,  Tsung-Yuan Hung ,  Chi-Cheng Yang ,  Ching-Hsing Hsieh

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H10L21/283

CPC分类号： H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/0332 ,  H01L21/31116

摘要： A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For each different etching mass, the TiN etching mask is not necessarily removed after etching; the silicon nitride etching mask is removed after etching; the oxide layer in the oxide/TiN etching mask is sacrificial layer.

摘要翻译： 一种制造通孔的方法，该通孔使用硬蚀刻掩模来蚀刻通孔。 在开始通孔蚀刻之前去除用于图案硬蚀刻掩模的光致抗蚀剂层。 硬蚀刻掩模包括TiN蚀刻掩模，氮化硅蚀刻掩模和氧化物/ TiN蚀刻掩模。 对于每个不同的蚀刻质量，TiN蚀刻掩模在蚀刻后不一定被去除; 蚀刻后去除氮化硅蚀刻掩模; 氧化物/ TiN蚀刻掩模中的氧化物层是牺牲层。

公开(公告)号：US6133114A

公开(公告)日：2000-10-17

申请号：US152450

申请日：1998-09-14

申请人： William Lu ,  Tsung-Yuan Hung

发明人： William Lu ,  Tsung-Yuan Hung

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. A liner oxide layer is formed over a side-wall of the trench in the substrate. An isolating layer by APCVD and an isolating layer by HDPCVD are sequentially formed over the substrate, in which the height of the CVD isolating layer within the trench is lower than the height of the hard masking layer. A CMP process is performed, using the hard masking layer as a polishing stop. The hard masking layer and the pad oxide layer are removed to accomplish the STI structure.

摘要翻译： 制造STI结构的方法包括在半导体衬底上依次形成衬垫氧化物层和硬掩模层。 通过在衬底上图案化在衬底中形成沟槽。 衬底氧化物层形成在衬底中的沟槽的侧壁上。 通过APCVD的绝缘层和通过HDPCVD的隔离层依次形成在衬底上，其中沟槽内的CVD隔离层的高度低于硬掩模层的高度。 使用硬掩模层作为抛光停止件来执行CMP处理。 去除硬掩模层和焊盘氧化物层以实现STI结构。

公开(公告)号：US6001708A

公开(公告)日：1999-12-14

申请号：US164288

申请日：1998-10-01

申请人： Ming-Tsung Liu ,  Tsung-Yuan Hung

发明人： Ming-Tsung Liu ,  Tsung-Yuan Hung

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76232 ,  H01L21/31111

摘要： A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer first formed over a semiconductor substrate. A trench is formed in the substrate. A first insulating layer is formed over the substrate. The surface of the first insulating layer within the trench is be between the hard masking layer surface and the semiconductor substrate surface. An insulating cap layer is formed over the first insulating layer with a hardness at least about as large as the hard masking layer. A second insulating layer is formed over the insulating cap layer. A chemical mechanical polishing (CMP) process is performed, using the hard masking layer as a polishing stop, to planarize over the substrate. A process of dipping the substrate into a HF acid solution is performed to remove the hard masking layer and the pad oxide layer, in which the process also simultaneously removes the remaining second insulating layer and the remaining insulating cap layer. The STI structure is accomplished with a significant avoidance of dishing and microscratch.

摘要翻译： 制造STI结构的方法包括首先在半导体衬底上形成的衬垫氧化物层和硬掩模层。 在衬底中形成沟槽。 在衬底上形成第一绝缘层。 沟槽内的第一绝缘层的表面位于硬掩模层表面和半导体衬底表面之间。 绝缘盖层形成在第一绝缘层之上，硬度至少与硬掩模层大约一样大。 在绝缘盖层上形成第二绝缘层。 使用硬掩模层作为抛光停止件进行化学机械抛光（CMP）处理，以在基板上平坦化。 进行将基板浸渍到HF酸溶液中的工序，以去除硬掩模层和焊盘氧化物层，其中该工艺还同时去除剩余的第二绝缘层和剩余的绝缘盖层。 STI结构的实现是大大避免了凹陷和显微纹理。

公开(公告)号：US5981325A

公开(公告)日：1999-11-09

申请号：US299255

申请日：1999-04-26

申请人： Tsung-Yuan Hung

发明人： Tsung-Yuan Hung

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864

摘要： A method of manufacturing a CMOS. A substrate is provided, wherein the substrate has a first conductive-type well, a second conductive-type well, an isolation structure formed therein, a first gate electrode on the second conductive-type well and a second gate electrode on the first conductive-type well. The first conductive-type well and the second conductive-type well are partly isolated from each other by the isolation structure. A first offset spacer is formed on a sidewall of the first and the second gate electrodes and a second offset spacer on a sidewall of the first offset spacer, wherein a portion of the first offset spacer extends on a surface of the substrate and the second offset spacer is on the portion of the first offset spacer. A first LDD region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the second offset spacer. The second offset spacer is removed to expose a portion of the first offset spacer extending on a portion of a surface of the substrate. A second LDD region having the second conductive type is formed in a portion of the first conductive-type well and exposed by the second gate electrode and the first offset spacer under the portion of the first offset spacer extending on a portion of a surface of the substrate. A spacer is formed on a sidewall of the first and the second gate electrodes. A first doped region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the spacer. A second doped region having the second conductive type is formed in a portion of the first conductive-type well exposed by the second gate electrode, the first offset spacer and the spacer.

摘要翻译： 一种制造CMOS的方法。 提供了一种衬底，其中衬底具有第一导电型阱，第二导电型阱，形成在其中的隔离结构，第二导电型阱上的第一栅电极和第一导电型阱上的第二栅电极， 类型很好。 第一导电型阱和第二导电型阱通过隔离结构部分地彼此隔离。 第一偏移间隔物形成在第一和第二栅电极的侧壁上，第二偏移间隔物形成在第一偏移间隔物的侧壁上，其中第一偏移间隔物的一部分在衬底的表面上延伸，第二偏移 间隔物位于第一偏移间隔物的部分上。 具有第一导电类型的第一LDD区形成在由第一栅电极，第一偏移间隔物和第二偏移间隔物暴露的第二导电类型阱的一部分中。 去除第二偏移间隔物以暴露在衬底表面的一部分上延伸的第一偏移间隔物的一部分。 具有第二导电类型的第二LDD区形成在第一导电类型阱的一部分中并且被第二栅极电极和第一偏移间隔物暴露在第一偏移间隔物的在第一导电类型阱的表面的一部分上的部分之下 基质。 间隔物形成在第一和第二栅电极的侧壁上。 具有第一导电类型的第一掺杂区域形成在由第一栅极电极，第一偏移间隔物和间隔物暴露的第二导电类型阱的一部分中。 具有第二导电类型的第二掺杂区形成在由第二栅电极，第一偏移间隔物和间隔物暴露的第一导电类型井的一部分中。

公开(公告)号：US06190999B1

公开(公告)日：2001-02-20

申请号：US09152360

申请日：1998-09-14

申请人： Tsung-Yuan Hung ,  William Lu

发明人： Tsung-Yuan Hung ,  William Lu

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for fabricating a shallow trench isolation (STI) structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. Then, the hard masking layer is removed to expose the pad oxide layer. An insulating layer is formed over the substrate to fill the trench. Using the pad oxide layer as a polishing stop, a CMP process is performed to polish the insulating layer until the pad oxide layer is exposed. The remained pad oxide within the trench is simultaneously planarized to have a planar top surface without dishing and microscratch. After the pad oxide is removed, the STI structure is accomplished.

摘要翻译： 一种制造浅沟槽隔离（STI）结构的方法包括在半导体衬底上依次形成焊盘氧化物层和硬掩模层。 通过在衬底上图案化在衬底中形成沟槽。 然后，去除硬掩模层以露出焊盘氧化物层。 在衬底上形成绝缘层以填充沟槽。 使用焊盘氧化物层作为抛光停止件，进行CMP工艺以抛光绝缘层，直到焊盘氧化物层露出。 沟槽内剩余的衬垫氧化物同时被平坦化以具有平坦的顶表面，而不会产生凹陷和显微纹理。 在去除衬垫氧化物之后，实现STI结构。

公开(公告)号：US5937298A

公开(公告)日：1999-08-10

申请号：US957811

申请日：1997-10-27

申请人： Tsung-Yuan Hung ,  Yao-Pi Hsu

发明人： Tsung-Yuan Hung ,  Yao-Pi Hsu

IPC分类号： H01L21/336 ,  H01L27/02

CPC分类号： H01L29/66659 ,  H01L27/0266 ,  H01L29/665

摘要： A method for forming electrostatic discharge protection devices that includes the steps of forming a transistor, which comprises a gate, a source region, a drain region, on a semiconductor substrate. Then, an insulating layer is formed over the transistor. Next, the insulating layer above the gate is removed, which represents one characteristic of this invention. Subsequently, a photolithographic processing operation is performed to form a photoresist layer over the substrate. The photoresist layer covers the insulating layer above the gate and the drain region while exposing the insulating layer above the source region. Thereafter, using the photoresist layer as a mask, the exposed insulating layer above the source region is removed. Next, the photoresist layer is removed. Finally, a self-aligned silicide processing operation is performed to form a silicide layer over the gate and the source region. Since no silicide layer is formed over the drain terminal, burnout of the drain terminal due to overheating can be avoided.

摘要翻译： 一种用于形成静电放电保护器件的方法，包括在半导体衬底上形成包括栅极，源极区域，漏极区域的晶体管的步骤。 然后，在晶体管上形成绝缘层。 接下来，去除栅极上方的绝缘层，这代表本发明的一个特征。 随后，进行光刻处理操作以在衬底上形成光致抗蚀剂层。 光致抗蚀剂层在栅极和漏极区域上方覆盖绝缘层，同时使源区域上方的绝缘层暴露。 此后，使用光致抗蚀剂层作为掩模，去除源区域上方的暴露的绝缘层。 接下来，去除光致抗蚀剂层。 最后，进行自对准的硅化物处理操作以在栅极和源极区域上形成硅化物层。 由于在漏极端子上没有形成硅化物层，所以可以避免由于过热引起的漏极端子的烧坏。