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公开(公告)号：US06819601B2
公开(公告)日：2004-11-16
申请号：US10454862
申请日：2003-06-05
Applicant: Jarrod Eliason , Bill Kraus , Hugh McAdams , Scott Summerfelt , Theodore S. Moise
Inventor： Jarrod Eliason , Bill Kraus , Hugh McAdams , Scott Summerfelt , Theodore S. Moise
IPC: G11C700
CPC classification number: G11C11/22
Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.
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公开(公告)号：US06864738B2
公开(公告)日：2005-03-08
申请号：US10337053
申请日：2003-01-06
Applicant: Xiao Hong Du , Jarrod Eliason , Yunchen Qiu , Bill Kraus
Inventor： Xiao Hong Du , Jarrod Eliason , Yunchen Qiu , Bill Kraus
CPC classification number: H02M3/073 , H02M2001/0032 , Y02B70/16
Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.
Abstract translation: 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 该CMOS升压器的一个关键思想是在每次存储器访问结束时使用NMOS FET（MN1）将升压电容器（C1）充电至VDD，并使用PMOS FET（MP1，MP2）将电压保持在 在待机期间输出VDD。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET的栅极通过小电容（C2）升压到VDD + Vthn以上，以在每次存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C2）通过其栅极连接到字线升压电容器的NMOSFET（MN2）预充电到VDD。 PMOS FET的栅极短路到其源极，以在升压期间将其关断。
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公开(公告)号：US07233194B2
公开(公告)日：2007-06-19
申请号：US10682125
申请日：2003-10-09
Applicant: Xiao Hong Du , Jarrod Eliason , Yunchen Qiu , Bill Kraus
Inventor： Xiao Hong Du , Jarrod Eliason , Yunchen Qiu , Bill Kraus
CPC classification number: H02M3/073 , H02M2001/0032 , Y02B70/16
Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.
Abstract translation: 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 CMOS升压器包括在每个存储器存取结束时将升压电容器（C 1）充电至VDD的NMOS FET（MN 1），并且包括PMOS FET（MP 1，MP 2），以将输出端的电压保持在VDD 待机时。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET（MN 1）的栅极通过小电容器（C 2）升压到VDD + Vthn以上，以在每个存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C 2）通过其栅极连接到字线升压电容器的NMOSFET（MN 2）预充电到VDD。 每个PMOS FET（MP 1，MP 2）的栅极短路到其源极，以在boostenig期间关闭。 晶体管（MP 3）有助于将NMOS FET（MN 1）升压到VDD以上。
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公开(公告)号：US06909318B2
公开(公告)日：2005-06-21
申请号：US10649405
申请日：2003-08-27
Applicant: Xiao Hong Du , Jarrod Eliason , Yunchen Qiu , Bill Kraus
Inventor： Xiao Hong Du , Jarrod Eliason , Yunchen Qiu , Bill Kraus
CPC classification number: H02M3/073 , H02M2001/0032 , Y02B70/16
Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.
Abstract translation: 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 CMOS升压器包括在每个存储器存取结束时将升压电容器（C 1）充电至VDD的NMOS FET（MN 1），并且包括PMOS FET（MP 1，MP 2），以将输出端的电压保持在VDD 待机时。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET（MN 1）的栅极通过小电容器（C 2）升压到VDD + Vthn以上，以在每个存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C 2）通过其栅极连接到字线升压电容器的NMOSFET（MN 2）预充电到VDD。 每个PMOS FET（MP 1，MP 2）的栅极短路，以在boostenig期间关闭源。 T晶体管（MP 3）有助于将NMOS FET（MN 1）升压到VDD以上。
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