公开(公告)号：US20120170348A1

公开(公告)日：2012-07-05

申请号：US13240252

申请日：2011-09-22

Applicant: Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

Inventor： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.

Abstract translation: 自定时读出放大器读缓冲器拉低预充电的高全局位线，然后将数据馈送到直接连接到位线的三态回写缓冲器。 该位线向强电介质电容器充电以在绕过感测放大器和铁电电容器之间的隔离开关旁路时写入逻辑“1”或“0”。 由于读出放大器使用接地位线检测，所以读缓冲器不会开始下拉全局位线直到读出放大器信号放大，这使得该读缓冲器的控制信号的定时非关键。 回写缓冲器使能定时也是从读出放大器自定时的。 因此，读取到强电介质存储单元的数据被局部控制，并且在从铁电存储单元读取数据之后迅速开始，从而允许快速循环时间。

公开(公告)号：US20070177422A1

公开(公告)日：2007-08-02

申请号：US11341083

申请日：2006-01-27

Applicant: Hugh McAdams

Inventor： Hugh McAdams

IPC: G11C11/34

CPC classification number: G11C11/22 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open. In a second storage phase the first and third switches are open and the second switch is closed, resulting in the cell voltage being boosted to the boost value.

Abstract translation: 一种用于存储产生表示位值的单元电压的电荷的存储单元，所述存储单元能够在读取所存储的电荷之后将单元电压升压到升压值。 存储单元包括连接在第一节点和地之间的第一电容器。 第二电容器连接在第二节点和地之间，第一开关连接在第一节点和第二节点之间。 第二开关和第三电容器串联连接在第一节点和第二节点之间，第二开关的端子连接到第一节点，第二开关的公共连接节点和第三电容器包括第三节点 。 第三个开关连接在第三个节点和地之间。 在操作中，在第一存储阶段中，第一和第三开关闭合，第二开关断开。 在第二存储阶段，第一和第三开关断开，第二开关闭合，导致电池电压升高到升压值。

公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

Applicant: Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

Inventor： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC: G11C11/22 ,  G11C11/24

CPC classification number: G11C11/22

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract translation: 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US08508974B2

公开(公告)日：2013-08-13

申请号：US13240420

申请日：2011-09-22

Applicant: Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

Inventor： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC: G11C11/22 ,  G11C5/06 ,  G11C7/00

CPC classification number: G11C11/2253 ,  G11C11/2275

Abstract: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.

Abstract translation: 铁电存储器件包括分配开关，其被配置为使铁电存储器件的铁电电容器的两侧短路。 因此，分流开关被配置为在从铁电电容器读取数据之前或之后从铁电电容器周围除去多余的电荷。 通过一种方法，分流开关被连接以对来自控制接入铁电电容器的相同线路的信号进行操作。 这样配置，例如通过施加预充电电压，通过消除用于否则从铁电电容器周围排出过量电荷的延迟来降低铁电存储器件的高性能周期时间。 分流开关还通过确保在读取周期期间过量的电荷不影响铁电电容器的读取来提高铁电存储器件的可靠性。

公开(公告)号：US20120170349A1

公开(公告)日：2012-07-05

申请号：US13240420

申请日：2011-09-22

Applicant: Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

Inventor： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC: G11C11/22

CPC classification number: G11C11/2253 ,  G11C11/2275

Abstract: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.

Abstract translation: 铁电存储器件包括分配开关，其被配置为使铁电存储器件的铁电电容器的两侧短路。 因此，分流开关被配置为在从铁电电容器读取数据之前或之后从铁电电容器周围除去多余的电荷。 通过一种方法，分流开关被连接以对来自控制接入铁电电容器的相同线路的信号进行操作。 这样配置，例如通过施加预充电电压，通过消除用于否则从铁电电容器周围排出过量电荷的延迟来降低铁电存储器件的高性能周期时间。 分流开关还通过确保在读取周期期间过量的电荷不影响铁电电容器的读取来提高铁电存储器件的可靠性。

公开(公告)号：US20070038805A1

公开(公告)日：2007-02-15

申请号：US11200390

申请日：2005-08-09

Applicant: Jarrod Eliason ,  Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams

Inventor： Jarrod Eliason ,  Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams

IPC: G06F12/00

CPC classification number: G11C29/848 ,  G11C11/22 ,  G11C29/816

Abstract: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.

Abstract translation: 公开了处理或处理有缺陷的“晶粒”或非易失性铁电存储器阵列的部分的方案。 在一个示例中，存储器的颗粒小于高和小于行宽的列。 当修复编程组发现部分的地址对应于失败的行地址和故障列地址时，对存储器部分执行替换操作。

公开(公告)号：US20050254282A1

公开(公告)日：2005-11-17

申请号：US10847412

申请日：2004-05-17

Applicant: Scott Summerfelt ,  Hugh McAdams

Inventor： Scott Summerfelt ,  Hugh McAdams

IPC: G11C5/14 ,  G11C11/22

CPC classification number: G11C11/22 ,  G11C5/147

Abstract: Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input (SABL/SABLB) prior to application of a plateline signal (PL) to the target cell capacitor (CFE). Where the sense amp input (SABL/SABLB) is initially precharged to zero volts, the extraction of charge provides a negative voltage on the data bitline (BL/BLB) when the plateline signal (PL) is applied, allowing adequate voltage to be applied across the cell capacitor (CFE) together with reduced plateline voltages (PL).

Abstract translation: 提供了方法（200）和系统（108），用于从将铁电信号（PL）施加到目标单元之前从感测放大器输入（SABL / SABLB）去除电荷的铁电存储器单元（106）读取数据 电容器（C FE）。 在感测放大器输入（SABL / SABLB）最初预充电到零伏的情况下，当施加平行线信号（PL）时，提取电荷在数据位线（BL / BLB）上提供负电压，允许施加足够的电压 跨越电池电容器（C SUB FE）以及降低的线路电压（PL）。

公开(公告)号：US20050041452A1

公开(公告)日：2005-02-24

申请号：US10644239

申请日：2003-08-19

Applicant: Hugh McAdams

Inventor： Hugh McAdams

IPC: G11C11/22 ,  G11C15/04 ,  G11C15/00

CPC classification number: G11C11/22 ,  G11C15/046

Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. A first data word is stored at a first address in a nonvolatile memory circuit 604. The first address 820 and the first data word 842 are stored in a volatile memory circuit 602. A first external address 608 is applied to the volatile memory circuit. The first external address is compared to the first address. The first data word is produced from the volatile memory circuit on a data bus 610 when the first external address matches the first address. The first data word is produced from the nonvolatile memory circuit on the data bus when the first external address does not match the first address.

Abstract translation: 公开了一种用于减少栅极氧化应力的存储电路和方法。 第一数据字存储在非易失性存储器电路604中的第一地址处。第一地址820和第一数据字842被存储在易失性存储器电路602中。第一外部地址608被施加到易失性存储器电路。 第一个外部地址与第一个地址进行比较。 当第一外部地址与第一地址匹配时，第一数据字由数据总线610上的易失性存储器电路产生。 当第一个外部地址与第一个地址不匹配时，第一个数据字由数据总线上的非易失性存储器电路产生。

公开(公告)号：US5790467A

公开(公告)日：1998-08-04

申请号：US756094

申请日：1996-11-25

Applicant: Brent S. Haukness ,  Hugh McAdams

Inventor： Brent S. Haukness ,  Hugh McAdams

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/00

CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C7/1051

Abstract: In a dynamic random access memory, the sense amplifiers associated with the storage cells have the direct sense circuitry (MNEW, MNWE.sub.--, MNRD, MNRD.sub.--) included therewith to minimize the effects of parasitic impedance. In addition, the Y-select circuits (MNYS, MNYS.sub.--) are combined with the read/write enable circuits (MNWE, MNWE.sub.--, MNRD, MNRD.sub.--) to eliminate a transistor pair, thereby reducing the required layout area. By locating the Y-select (MNYS, MNYS.sub.--) circuits between the sense amplifier MNWE, MNWE.sub.--, MNRD, MNRD.sub.--) and the local input/output lines (LIO, LIO.sub.--), the WRITE-ENABLE and the READ-ENABLE signals can be combined in a single signal.

Abstract translation: 在动态随机存取存储器中，与存储单元相关联的读出放大器具有包括在其中的直接感测电路（MNEW，MNWE-，MNRD，MNRD-），以最小化寄生阻抗的影响。 此外，Y选择电路（MNYS，MNYS-）与读/写使能电路（MNWE，MNWE-，MNRD，MNRD-）组合以消除晶体管对，从而减少所需的布局面积。 通过在读出放大器MNWE，MNWE-，MNRD，MNRD-）和本地输入/输出线（LIO，LIO-）之间定位Y选择（MNYS，MNYS-）电路，写入使能和READ-ENABLE 信号可以组合在单个信号中。

公开(公告)号：US08724367B2

公开(公告)日：2014-05-13

申请号：US13243875

申请日：2011-09-23

Applicant: Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

Inventor： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC: G11C11/22

CPC classification number: G11C11/1673 ,  G11C11/1677 ,  G11C11/22 ,  G11C29/12 ,  G11C29/30 ,  G11C2029/1202 ,  G11C2029/5002

Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.

Abstract translation: FRAM设备可以包括读出放大器，至少第一位单元，第一控制线和第二控制线。 第一位单元可以具有通过第一隔离器和与第一隔离器不同的第二隔离器连接到读出放大器的互补位线连接到读出放大器的位线。 第一控制线可以连接到并控制上述第一隔离器。 并且第二控制线可以连接到并控制第二隔离器，使得第二隔离器相对于第一隔离器被独立地控制，以便于测试设备。