公开(公告)号：US11372620B1

公开(公告)日：2022-06-28

申请号：US17399459

申请日：2021-08-11

Applicant: Jarrod Eliason

Inventor： Jarrod Eliason

IPC: G06F3/16 ,  G06F1/16 ,  G06Q10/10 ,  G06F3/0488 ,  G06F3/01

Abstract: An exemplary voice monitoring system includes a wearable voice monitor and an auxiliary device such as a smart phone. The wearable monitor incorporates a wake-on-sound microphone, a vibration motor, and a microcontroller within a small, discreet enclosure. The enclosure can be hung from a necklace chain or affixed to clothing, like a piece of jewelry. The jewelry appearance is enhanced by a removable decorative piece. The microcontroller wakes up in response to a wake signal from the microphone when a voice sound of a wearer is detected. The microcontroller initiates measurements to determine if the voice sound meets preconfigured criteria and activates the vibration motor to alert the wearer. Sound criteria resulting in vibratory alerts are contained in a user-specific schedule tailored according to time of day and day of week. The smart phone can remotely create customized schedules and transmit them to the monitor.

公开(公告)号：US06894549B2

公开(公告)日：2005-05-17

申请号：US10613427

申请日：2003-07-03

Applicant: Jarrod Eliason

Inventor： Jarrod Eliason

IPC: G11C11/22 ,  G11C19/00 ,  G11C19/28 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/105 ,  H03K3/356 ,  H03K3/45 ,  H03K19/185 ,  H03K3/037 ,  H03K3/12

CPC classification number: G11C11/22 ,  G11C19/005 ,  H03K3/356008 ,  H03K3/45

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract translation: 诸如SR触发器，JK触发器，D型触发器，主从触发器，并行和串行移位寄存器等各种逻辑元件被转换为能够保持 即使通过铁电电容器和支持电路的战略添加来消除或中断外部电源，电流输出逻辑状态。 在每种情况下，在逻辑元件内识别交叉耦合读出放大器的构建块，并且基本单元被修改和/或优化用于感测性能。

公开(公告)号：US06430093B1

公开(公告)日：2002-08-06

申请号：US09864858

申请日：2001-05-24

Applicant: Jarrod Eliason ,  William F. Kraus

Inventor： Jarrod Eliason ,  William F. Kraus

IPC: G11C700

CPC classification number: G11C8/08 ,  G11C11/22

Abstract: A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

Abstract translation: 一种用于使用NAND-INVERT电路来控制铁电升压电容器的一个电极的铁电存储器的升压电路。 电容器的另一个节点连接到要升压的节点，可以耦合到字线。 NAND电路具有两个输入，一个耦合到字线，另一个用于接收定时信号。 定时输入上升以启动升压操作，并降低以启动升压电压的去除。 只有在低逻辑电平“0”的任何字线都会影响存储器阵列中的选定字线，从而将变频器输出保持为低电平。 第二实施例将第二N沟道晶体管与逆变器的N沟道晶体管串联，以允许选择浮置逆变器输出，如果希望在其第一向上转换期间更快速地驱动字线高电平。

公开(公告)号：US20070090461A1

公开(公告)日：2007-04-26

申请号：US11567873

申请日：2006-12-07

Applicant: Jarrod Eliason ,  Glen Fox ,  Richard Bailey

Inventor： Jarrod Eliason ,  Glen Fox ,  Richard Bailey

IPC: H01L23/62

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/20 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract translation: 提出了铁电存储器单元（3），其中单元电容器（R）被集成到单元电容器（C）中，以在单元（3）不是单元电容器（3）时抑制电池存储节点（SN）处的电荷累积或电荷损耗 在避免存储器单元访问操作的显着中断的同时被访问。 提供方法（100,200）用于制造其中并联电阻（R）集成在电容器铁电材料（20）中或在形成的封装层（46）中的铁电存储器单元（3）和铁电电容器（C） 超过图案化电容器结构（C）。

公开(公告)号：US20060118841A1

公开(公告)日：2006-06-08

申请号：US11004708

申请日：2004-12-03

Applicant: Jarrod Eliason ,  Glen Fox ,  Richard Bailey

Inventor： Jarrod Eliason ,  Glen Fox ,  Richard Bailey

IPC: H01L29/94

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/20 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: Ferroelectric memory cells (3) are presented, in which a cell resistor (R) is integrated into the cell capacitor (C) to inhibit charge accumulation or charge loss at the cell storage node (SN) when the cell (3) is not being accessed while avoiding significant disruption of memory cell access operations. Methods (100, 200) are provided for fabricating ferroelectric memory cells (3) and ferroelectric capacitors (C), in which a parallel resistance (R) is integrated in the capacitor ferroelectric material (20) or in an encapsulation layer (46) formed over the patterned capacitor structure (C).

Abstract translation: 提出了铁电存储器单元（3），其中单元电容器（R）被集成到单元电容器（C）中，以在单元（3）不是单元电容器（3）时抑制电池存储节点（SN）处的电荷累积或电荷损耗 在避免存储器单元访问操作的显着中断的同时被访问。 提供方法（100,200）用于制造其中并联电阻（R）集成在电容器铁电材料（20）中或在形成的封装层（46）中的铁电存储器单元（3）和铁电电容器（C） 超过图案化电容器结构（C）。

公开(公告)号：US20060098471A1

公开(公告)日：2006-05-11

申请号：US10985137

申请日：2004-11-10

Applicant: Jarrod Eliason

Inventor： Jarrod Eliason

IPC: G11C11/22 ,  G11C7/10

CPC classification number: G11C11/22 ,  G11C7/20

Abstract: Configuration data is stored in one or more rows of non-volatile ferroelectric memory cells, where these rows are formed adjacent to rows of a primary memory array. The primary memory array includes non-volatile ferroelectric memory cells, and the memory cells of the array are substantially the same in construction to the cells of the configuration data rows. This allows at least some of the circuitry utilized to access data from the primary array to be utilized to access the configuration data, which promotes an efficient use of resources among other things. Additionally, the configuration data can be transferred to volatile registers serially at startup to simplify routing and design and thereby conserve space. The volatile registers are operatively associated with configuration data circuitry that makes use of the configuration data at startup or later time(s).

Abstract translation: 配置数据存储在一行或多行非易失性铁电存储器单元中，其中这些行与主存储器阵列的行相邻地形成。 主存储器阵列包括非易失性铁电存储器单元，并且阵列的存储器单元在结构上与配置数据行的单元基本相同。 这允许用于访问来自主阵列的数据的至少一些电路被用于访问配置数据，这促进了其他事物之间的资源的有效利用。 此外，配置数据可以在启动时串行传输到易失性寄存器，以简化路由和设计，从而节省空间。 易失性寄存器与配置数据电路可操作地相关联，配置数据电路在启动时或稍后时间使用配置数据。

公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

Applicant: Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

Inventor： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC: G11C11/22 ,  G11C11/24

CPC classification number: G11C11/22

Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

Abstract translation: 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US06864738B2

公开(公告)日：2005-03-08

申请号：US10337053

申请日：2003-01-06

Applicant: Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

Inventor： Xiao Hong Du ,  Jarrod Eliason ,  Yunchen Qiu ,  Bill Kraus

IPC: H02M3/07 ,  G05F1/10 ,  G05F3/02

CPC classification number: H02M3/073 ,  H02M2001/0032 ,  Y02B70/16

Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. One key idea in this CMOS booster is to use a NMOS FET (MN1) to charge the boosting capacitor (C1) to VDD at the end of each memory access and to use a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of the PMOS FET is shorted to its source to turn it off during boosting.

Abstract translation: 本发明是一种新的CMOS升压器（20），其具有可用于存储器中以将字线电压升高到高于VDD或其它升压应用的输出。 该CMOS升压器的一个关键思想是在每次存储器访问结束时使用NMOS FET（MN1）将升压电容器（C1）充电至VDD，并使用PMOS FET（MP1，MP2）将电压保持在 在待机期间输出VDD。 通过使用这种组合，字线上升时间，增强器的尺寸和访问期间的功耗显着降低。 NMOS FET的栅极通过小电容（C2）升压到VDD + Vthn以上，以在每次存储器访问结束时将字线升压电容器充电到VDD。 小电容器（C2）通过其栅极连接到字线升压电容器的NMOSFET（MN2）预充电到VDD。 PMOS FET的栅极短路到其源极，以在升压期间将其关断。

公开(公告)号：US06650158B2

公开(公告)日：2003-11-18

申请号：US10076058

申请日：2002-02-12

Applicant: Jarrod Eliason

Inventor： Jarrod Eliason

IPC: H03K3289

CPC classification number: G11C11/22 ,  G11C19/005 ,  H03K3/356008 ,  H03K3/45

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

公开(公告)号：US6141237A

公开(公告)日：2000-10-31

申请号：US351563

申请日：1999-07-12

Applicant: Jarrod Eliason ,  William F. Kraus

Inventor： Jarrod Eliason ,  William F. Kraus

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H03K3/356

CPC classification number: G11C11/22

Abstract: A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.

Abstract translation: 非挥发性铁电锁存器包括读出放大器，其具有耦合到位线节点的至少一个输入/输出，耦合在板状线节点和位线节点之间的铁电存储电容器以及耦合到该位线线路节点的负载元件 位线节点。 感测放大器还包括耦合到第二位线节点的第二输入/输出，并且锁存器还包括耦合在第二板状线节点和第二位正弦节点之间的第二铁电存储电容器，以及耦合到第二负载元件的第二负载元件 到第二位线节点。 负载元件包括动态的，开关的铁电电容器，静态的，非开关的铁电电容器，线性电容器或甚至电阻负载。