利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

4 条记录 (耗时 0.009 秒)

    Binder Composition and Method Thereof
    1.
    发明公开
    Binder Composition and Method Thereof 审中-公开

    公开(公告)号：US20240317645A1

    公开(公告)日：2024-09-26

    申请号：US18123375

    申请日：2023-03-20

    申请人： Binish Desai

    发明人： Binish Desai

    IPC分类号： C04B26/28 ,  C04B26/26

    CPC分类号： C04B26/28 ,  C04B26/26

    摘要： A dry binder composition comprised of biopolymers, an emulsifier and at least one starch, plasticizer, mineral admixture, and filler material is provided. Furthermore, methods of manufacturing a liquid binder composition that can be used to make various bricks, pavers, flooring and concrete compositions is disclosed. I one embodiment a concrete composition made from combining the binder composition and garbage of bituminous derivatives is disclosed.

    Method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack
    3.
    发明申请
    Method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack 审中-公开
    用于有效地分配和释放存储在存储器堆栈中的交错数据的方法和装置

    公开(公告)号：US20050254441A1

    公开(公告)日：2005-11-17

    申请号：US10925424

    申请日：2004-08-25

    申请人： Alan Levi ,  Douglas Castor ,  George McClellan ,  Binish Desai

    发明人： Alan Levi ,  Douglas Castor ,  George McClellan ,  Binish Desai

    IPC分类号： H04B7/00 ,  H04L12/56 ,  H04W28/14 ,  H04L12/54

    CPC分类号： H04L47/14 ,  H04L47/50 ,  H04L47/564 ,  H04L47/621 ,  H04W28/14

    摘要： A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    摘要翻译： 一种用于有效地分配和释放存储在存储器堆栈中的交错数据的方法和装置。 该装置包括处理器和包括至少一个存储器堆栈的存储器。 处理器接收和交织多个数据块。 为特定传输信道（TrCH）分配每个数据块，并具有指定的传输定时间隔（TTI）。 处理器基于每个数据块的TTI将交织的数据块存储在存储器堆栈中，使得具有较大TTI的数据块较早地分配给存储器堆栈，并且比具有较小TTI的数据块更早地从堆栈中释放 。 在一个实施例中，存储器包括用于公共/共享上行链路信道的第一存储器堆栈，用于专用上行链路信道的第二存储器堆栈，用于公共/共享下行链路信道的第三存储器堆栈以及用于专用下行链路信道的第四存储器堆栈。