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    Pipeline architecture for maximum a posteriori (MAP) decoders
    7.
    发明授权
    Pipeline architecture for maximum a posteriori (MAP) decoders 失效
    最大后验（MAP）解码器的管道架构

    公开(公告)号：US08316285B2

    公开(公告)日：2012-11-20

    申请号：US13045041

    申请日：2011-03-10

    申请人： Edward L. Hepler ,  Michael F. Starsinic

    发明人： Edward L. Hepler ,  Michael F. Starsinic

    IPC分类号： H03M13/00

    CPC分类号： H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

    摘要： Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.

    摘要翻译： 公开了进行数据位纠错的方法和装置。 可以在第一窗口期间执行前向度量计算，以生成第一组计算数据。 来自正向计算的第一组计算数据可以存储在存储器位置中。 可以在第二窗口期间执行前向度量计算，以生成第二组计算数据。 可以从存储器位置读取第一组计算数据，并且将第二组计算数据存储在相同的存储单元中。 计算数据的第一组可用于计算反向度量。

    Pipeline architecture for maximum a posteriori (MAP) decoders
    8.
    发明授权
    Pipeline architecture for maximum a posteriori (MAP) decoders 失效
    最大后验（MAP）解码器的管道架构

    公开(公告)号：US07181670B2

    公开(公告)日：2007-02-20

    申请号：US11219986

    申请日：2005-09-06

    申请人： Edward L. Hepler ,  Michael F. Starsinic

    发明人： Edward L. Hepler ,  Michael F. Starsinic

    IPC分类号： H03M13/00 ,  H03M13/03

    CPC分类号： H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

    摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

    摘要翻译： 流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。 一旦为解码器的第一滑动窗口计算了前向量度，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。 当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。 用于计算外在值的每个前向量度被写入相同的存储器位置。 计算可以反转，首先计算反向度量，然后是反向度量计算。 虽然为turbo解码器开发的这种架构，但是所有的卷积码都可以使用本发明的MAP算法。

    PIPELINE ARCHITECTURE FOR MAXIMUM A POSTERIORI (MAP) DECODERS
    9.
    发明申请
    PIPELINE ARCHITECTURE FOR MAXIMUM A POSTERIORI (MAP) DECODERS 失效
    最大的一个POSISIORI（MAP）解码器的管道结构

    公开(公告)号：US20110271166A1

    公开(公告)日：2011-11-03

    申请号：US13045041

    申请日：2011-03-10

    申请人： Edward L. Hepler ,  Michael F. Starsinic

    发明人： Edward L. Hepler ,  Michael F. Starsinic

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

    摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

    摘要翻译： 流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。 一旦为其解码器的第一滑动窗口计算了前向度量，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。 当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。 用于计算外在值的每个前向量度被写入同一个存储单元。 计算可以反转，首先计算反向度量，然后是反向度量计算。 虽然该架构是为turbo解码器开发的，但是所有的卷积码都可以使用本发明的MAP算法。

    Pipeline architecture for maximum a posteriori (MAP) decoders
    10.
    发明授权
    Pipeline architecture for maximum a posteriori (MAP) decoders 失效
    最大后验（MAP）解码器的管道架构

    公开(公告)号：US06961921B2

    公开(公告)日：2005-11-01

    申请号：US10037609

    申请日：2002-01-02

    申请人： Edward L. Hepler ,  Michael F. Starsinic

    发明人： Edward L. Hepler ,  Michael F. Starsinic

    IPC分类号： G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  H03M13/03

    CPC分类号： H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

    摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

    摘要翻译： 流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。 一旦为解码器的第一滑动窗口计算了前向量度，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。 当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。 用于计算外在值的每个前向量度在相同的时钟边沿从存储器读取，该时钟边沿将新的前向量度写入相同的存储器位置。 虽然该架构是为turbo解码器开发的，但是所有的卷积码都可以使用本发明的MAP算法。