Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect
    1.
    发明授权
    Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect 有权
    芯片到布线接口,单个金属合金层应用于铜互连表面

    公开(公告)号:US06573606B2

    公开(公告)日:2003-06-03

    申请号:US09881444

    申请日:2001-06-14

    IPC分类号: H01L2144

    摘要: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

    摘要翻译: 在本发明中,提供了电隔离的铜互连结构界面,其涉及单个约50-300A厚的合金覆盖层,其控制互连部件的扩散和电迁移并且降低互连的整体有效介电常数; 封盖层被本领域中称为材料所包围的材料包围,其可以为随后的反应离子蚀刻操作提供抗蚀剂,并且还提供了在结构界面的制造中涉及无电沉积的相互依赖的工艺步骤。 本发明中的单层合金金属阻挡层是一般型AXY的合金,其中A是从钴(Co)和镍(Ni)中取出的金属,X是取自钨(W ),锡(Sn)和硅(Si),Y是从磷(P)和硼(B)取代的成员; 厚度在50至300埃的范围内。