利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

52 条记录 (耗时 0.032 秒)

    Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect
    1.
    发明授权
    Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect 有权
    芯片到布线接口，单个金属合金层应用于铜互连表面

    公开(公告)号：US06573606B2

    公开(公告)日：2003-06-03

    申请号：US09881444

    申请日：2001-06-14

    申请人： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

    发明人： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

    IPC分类号： H01L2144

    CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

    摘要翻译： 在本发明中，提供了电隔离的铜互连结构界面，其涉及单个约50-300A厚的合金覆盖层，其控制互连部件的扩散和电迁移并且降低互连的整体有效介电常数; 封盖层被本领域中称为材料所包围的材料包围，其可以为随后的反应离子蚀刻操作提供抗蚀剂，并且还提供了在结构界面的制造中涉及无电沉积的相互依赖的工艺步骤。 本发明中的单层合金金属阻挡层是一般型AXY的合金，其中A是从钴（Co）和镍（Ni）中取出的金属，X是取自钨（W ），锡（Sn）和硅（Si），Y是从磷（P）和硼（B）取代的成员; 厚度在50至300埃的范围内。

    REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF CU WIRES BY SURFACE COATING
    2.
    发明申请
    REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF CU WIRES BY SURFACE COATING 审中-公开
    通过表面涂层降低CU电线的电导率和受压感应迁移

    公开(公告)号：US20090142924A1

    公开(公告)日：2009-06-04

    申请号：US12341856

    申请日：2008-12-22

    申请人： Chao-Kun Hu ,  Robert Rosenberg ,  Judith Marie Rubino ,  Carlos Juan Sambucetti ,  Anthony Kendall Stamper

    发明人： Chao-Kun Hu ,  Robert Rosenberg ,  Judith Marie Rubino ,  Carlos Juan Sambucetti ,  Anthony Kendall Stamper

    IPC分类号： H01L21/441

    CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76864 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

    摘要翻译： 本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。 该涂层足够薄，以便消除对通过抛光的附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已被发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热 压力消除。 此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。 自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。 提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。 尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。

    EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS
    7.
    发明申请
    EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS 有权
    电气保险丝应用的有效互连结构

    公开(公告)号：US20110092031A1

    公开(公告)日：2011-04-21

    申请号：US12976445

    申请日：2010-12-22

    申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

    发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

    IPC分类号： H01L21/283

    CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

    摘要翻译： 提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。 互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。 熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。 电介质覆盖层位于电介质材料和导电材料的顶部。 在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。 因此，当电流被提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

    Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
    8.
    发明授权
    Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via 失效
    使用垂直向上延伸的虚拟通孔增加IC中的电迁移寿命和电流密度

    公开(公告)号：US07439173B2

    公开(公告)日：2008-10-21

    申请号：US11869044

    申请日：2007-10-09

    申请人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

    发明人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

    摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

    INCREASING ELECTROMIGRATION LIFETIME AND CURRENT DENSITY IN IC USING VERTICALLY UPWARDLY EXTENDING DUMMY VIA
    9.
    发明申请
    INCREASING ELECTROMIGRATION LIFETIME AND CURRENT DENSITY IN IC USING VERTICALLY UPWARDLY EXTENDING DUMMY VIA 失效
    使用垂直延伸的直流电源增加IC中的电寿命和电流密度

    公开(公告)号：US20080026567A1

    公开(公告)日：2008-01-31

    申请号：US11869044

    申请日：2007-10-09

    申请人： Stephen Greco ,  Chao-Kun Hu ,  Paul McLaughlin

    发明人： Stephen Greco ,  Chao-Kun Hu ,  Paul McLaughlin

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

    摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。