Abstract:
A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.
Abstract:
A general purpose, software-controlled central processor (CP) can be augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, a packet deconstructor, a search engine, and a packet editor. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability.
Abstract:
Methods and apparatus for providing a network data switch and buffer system are disclosed. In a switch having a memory associated therewith, the memory including a general memory and a plurality of dedicated memory segments, the general memory being available to a plurality of users associated with one or more network devices and each one of the plurality of dedicated memory segments being associated with one of the plurality of users, a method of storing data includes receiving data from a source network device connected to the switch. The data is then stored in a data buffer so that a portion of one of the plurality of dedicated memory segments is allocated when the general memory has been depleted.
Abstract:
A computer bus adapter device which is coupled to a true parallel computer bus is automatically set to a pre-determined configuration in response to configuration data provided to the bus by a host process. During a set-up portion of an initialization procedure, the adapter device recognizes a data sequence and uses information based on the recognized data sequence to configure itself to respond to its host process. In a specific embodiment, the desired configuration information is stored in non-volatile storage associated with the host process, such as a magnetic file or a non-volatile random access memory.
Abstract:
According to one general aspect, a method may include receiving at least a portion of a packet of data by an ingress device. The method may include determining an egress device to receive the packet. In some embodiments, the method may include dividing the received portion of the packet into a plurality of segments. The method may include editing, for each segment, a header to include an address field that indicates the address of the egress device, wherein the header is associated with a current segment. The method may include, for each segment, editing the header to include a next link field that indicates a link that will be used to transmit the next segment of the packet. The method may also include transmitting the current segment and header to the egress device via the link indicated in the next link field of the header of a preceding segment.
Abstract:
The present invention consists of a general purpose, software-controlled central processor (CP) augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, which provides the central processor with a numerical summary of the packet format; a packet deconstructor, which extracts designated fields from the packet the positions of which are determined by the central processor according to the packet format; a search engine, which is supplied a lookup index by and returns its results to the central processor; and a packet editor which modifies the packet as determined by the central processor using (in part) information returned from other peripherals. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability: rather than having to modify a circuit or system design in an ASIC or other hardware, new packet processing applications may be accommodated through the development of new software and its deployment in the central and/or peripheral processors.
Abstract:
According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.
Abstract:
According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.
Abstract:
According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.
Abstract:
According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.