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公开(公告)号:US06974978B1
公开(公告)日:2005-12-13
申请号:US09262458
申请日:1999-03-04
申请人: Brian D. Possley
发明人: Brian D. Possley
IPC分类号: H01L27/02 , H01L27/118 , H01L29/73
CPC分类号: H01L27/118 , H01L27/0207
摘要: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.
摘要翻译: 简而言之,根据本发明的一个实施例,集成电路包括:门阵列结构。 门阵列结构包括具有多个N型扩散区和P型扩散区的半导体衬底。 扩散区域具有部分覆盖多晶硅着陆点以形成N型和P型晶体管。 这些区域相对大小以形成两个不同的晶体管尺寸,较小的N型和P型晶体管以及较大的N型和P型晶体管。
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公开(公告)号:US07327370B2
公开(公告)日:2008-02-05
申请号:US11174662
申请日:2005-07-06
申请人: Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
发明人: Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
摘要: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译: 存储器控制器集线器包括适于对数据执行图形操作的图形子系统,以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。
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公开(公告)号:US07116331B1
公开(公告)日:2006-10-03
申请号:US09644967
申请日:2000-08-23
申请人: Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
发明人: Brian D. Possley , David M. Puffer , Kurt B. Robinson , Ray Askew , James S. Chapple , Thomas E. Dever, II
IPC分类号: G06F13/14
摘要: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
摘要翻译: 存储器控制器集线器包括适于对数据执行图形操作的图形子系统,以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。
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公开(公告)号:US06753209B2
公开(公告)日:2004-06-22
申请号:US09902907
申请日:2001-07-10
申请人: Brian D. Possley
发明人: Brian D. Possley
IPC分类号: H01L2182
CPC分类号: H01L27/118 , H01L27/0207
摘要: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.
摘要翻译: 简而言之,根据本发明的一个实施例,集成电路包括:门阵列结构。 门阵列结构包括具有多个N型扩散区和P型扩散区的半导体衬底。 扩散区域具有部分覆盖多晶硅着陆点以形成N型和P型晶体管。 这些区域相对大小以形成两个不同的晶体管尺寸,较小的N型和P型晶体管以及较大的N型和P型晶体管。
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