公开(公告)号：US5937423A

公开(公告)日：1999-08-10

申请号：US773168

申请日：1996-12-26

申请人： Kurt B. Robinson

发明人： Kurt B. Robinson

IPC分类号： G06F3/06 ,  G11C16/10 ,  G06F12/02

CPC分类号： G06F3/0607 ,  G06F3/0632 ,  G06F3/0689 ,  G11C16/10 ,  G11C2216/20

摘要： A flash EEPROM memory device including a memory array having a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash storage device, and a register interface for receiving data and commands addressed to the blocks of flash EEPROM memory devices and generating signals for affecting the purpose of the commands in the device, the interface including a command register for receiving commands and a plurality of registers for providing the data stored in the query memory as output.

摘要翻译： 一种闪存EEPROM存储器件，包括具有布置成以行和列进行访问的多个快闪EEPROM存储器单元的存储器阵列，存储定义闪存存储器件的特性的数据的查询存储器，以及用于接收数据和命令的寄存器接口 寻址到快速EEPROM存储器件的块并且产生用于影响器件中命令目的的信号，该接口包括用于接收命令的命令寄存器和用于提供存储在查询存储器中的数据作为输出的多个寄存器。

公开(公告)号：US5802553A

公开(公告)日：1998-09-01

申请号：US574646

申请日：1995-12-19

申请人： Kurt B. Robinson ,  Clark S. Thurlo

发明人： Kurt B. Robinson ,  Clark S. Thurlo

IPC分类号： G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C29/00 ,  G06F12/00

CPC分类号： G11C29/765 ,  G06F11/1072 ,  G06F3/0608 ,  G06F3/0643 ,  G06F3/0679 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641 ,  G11C29/00

摘要： A storage system contains a solid state disk drive having a plurality of memory cells to store the files, including file system control information and data. In a high density mode, the solid state disk drive stores more than one bit per memory cell, and in a reliable mode, the solid state disk drive stores one bit per cell. A file configuration system stores file system control information in the reliable mode and stores data, when specified, in the high density mode. The file configuration system includes a multi-level cell extension unit that generates commands to the memory cells. A data compression unit is provided to compress file data. A block size for the data compression unit is calculated in accordance with the number of bits per cell stored in the high density mode. The file configuration system further includes an error detection and correction (EDC) unit to detect and correct data stored in the high density mode. The storage system may be implemented to operate with the personal computer memory card industry association (PCMCIA) standard.

摘要翻译： 存储系统包含具有存储文件的多个存储单元的固态磁盘驱动器，包括文件系统控制信息和数据。 在高密度模式下，固态磁盘驱动器每个存储单元存储多于一个位，并且在可靠模式下，固态磁盘驱动器存储每个单元一位。 文件配置系统将文件系统控制信息存储在可靠模式中，并且在指定的情况下以高密度模式存储数据。 文件配置系统包括向存储器单元生成命令的多级单元扩展单元。 提供数据压缩单元来压缩文件数据。 根据以高密度模式存储的每个单元的比特数来计算数据压缩单元的块大小。 文件配置系统还包括用于检测和校正以高密度模式存储的数据的错误检测和校正（EDC）单元。 存储系统可以被实现为与个人计算机存储卡行业协会（PCMCIA）标准一起操作。

公开(公告)号：US5630093A

公开(公告)日：1997-05-13

申请号：US635030

申请日：1996-04-19

申请人： Gerald S. Holzhammer ,  Kurt B. Robinson

发明人： Gerald S. Holzhammer ,  Kurt B. Robinson

IPC分类号： G06F3/08 ,  G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G11C16/02 ,  G11C17/00

CPC分类号： G06F3/0601 ,  G06F12/0246 ,  G06F2003/0694

摘要： A non-volatile semiconductor memory that is erased in blocks is described. The non-volatile semiconductor memory includes an active block for storing first data and a reserve block for storing second data. The second data is a copy of the first data. The copy is made during a clean-up operation prior to erasure of the active block. The non-volatile semiconductor memory also includes a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory.

摘要翻译： 描述了以块为单位擦除的非易失性半导体存储器。 非易失性半导体存储器包括用于存储第一数据的活动块和用于存储第二数据的预留块。 第二个数据是第一个数据的副本。 在擦除活动块之前，在清理操作期间进行复印。 非易失性半导体存储器还包括用于将分配单元的逻辑地址映射到非易失性半导体存储器内的扇区的物理地址的映射表。

公开(公告)号：US5574879A

公开(公告)日：1996-11-12

申请号：US541522

申请日：1995-10-10

申请人： Steven E. Wells ,  Kurt B. Robinson

发明人： Steven E. Wells ,  Kurt B. Robinson

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/56 ,  G11C2211/5641 ,  G11C8/00

摘要： A memory system contains memory cells for storing multiple threshold levels to represent storage of "n" bits of data. The memory system includes an address buffer for generating a plurality of physical addresses such that each physical address uniquely identifies a memory location for "j" memory cells. In order to address a portion of the "n" bits identified by a single physical address, the address buffer generates a multi-level cell (MLC) address. The memory system also contains a switch control for permitting selection a multi-level cell (MLC) mode and a standard cell mode. A select circuit permits reading a single bit per cell when the memory operates in the standard cell mode, and permits reading multiple bits of data per memory cell when the memory operates in the multi-level cell mode. The addressing scheme of the present invention maintains address coherency by exhibiting a n:1 correspondence between memory locations and the physical addresses when operating in the MLC mode, and by exhibiting a 1:1 correspondence between memory space and the physical addresses when operating in the standard cell mode.

摘要翻译： 存储器系统包含用于存储多个阈值电平的存储器单元，以表示“n”位数据的存储。 存储器系统包括用于生成多个物理地址的地址缓冲器，使得每个物理地址唯一地标识“j”个存储器单元的存储器位置。 为了寻址由单个物理地址标识的“n”位的一部分，地址缓冲器生成多级单元（MLC）地址。 存储器系统还包含用于允许选择多级单元（MLC）模式和标准单元模式的开关控制。 当存储器以标准单元模式运行时，选择电路允许每单元读取单个位，并且当存储器以多电平单元模式运行时，允许每个存储单元读取多个位数据。 本发明的寻址方案通过在以MLC模式操作时通过表现出存储器位置与物理地址之间的1对应关系来维持地址一致性，并且当在标准中操作时通过显示存储器空间和物理地址之间的1：1对应关系 单元格模式。

公开(公告)号：US5428566A

公开(公告)日：1995-06-27

申请号：US144196

申请日：1993-10-27

申请人： Kurt B. Robinson

发明人： Kurt B. Robinson

IPC分类号： G11C16/22 ,  G11C5/06 ,  G11C16/06

CPC分类号： G11C16/22

摘要： A memory card includes a plurality of nonvolatile memories, each having a pad for applying a busy signal indicating that a respective memory is busy and a circuit for coupling the busy signal to the pad. The pad of each memory is coupled to a node external to the memories. A resistive circuit is used for coupling a first voltage to the node. When each of the memories does not output the busy signal at the pad, the node assumes a first voltage. When the pad of at least one of the memories outputs the busy signal, the node assumes a ground voltage. An output pin is used for supplying a card busy output signal when at least one of the memories is indicated busy and an input pin is coupled to the node for receiving the card busy output signal at the node. A pass logic is coupled to the input and output pins for passing the card busy output signal directly from the input pin to the output pin. Each of the memories also includes an input pad for receiving a global power down control signal and a register for receive a software power down control signal. A logic gate is used to allow either of the signals to pass.

摘要翻译： 存储卡包括多个非易失性存储器，每个非易失存储器具有用于施加指示相应存储器占线的忙信号的焊盘和用于将忙信号耦合到焊盘的电路。 每个存储器的焊盘耦合到存储器外部的节点。 电阻电路用于将第一电压耦合到节点。 当每个存储器不在该焊盘处输出忙信号时，节点承担第一电压。 当至少一个存储器的焊盘输出忙信号时，节点呈现接地电压。 当至少一个存储器被指示为忙并且输入引脚耦合到节点以接收该节点处的卡忙输出信号时，输出引脚用于提供卡忙输出信号。 传递逻辑耦合到输入和输出引脚，用于将卡忙输出信号直接从输入引脚传递到输出引脚。 每个存储器还包括用于接收全局掉电控制信号的输入焊盘和用于接收软件掉电控制信号的寄存器。 逻辑门用于允许任一信号通过。

公开(公告)号：US5422855A

公开(公告)日：1995-06-06

申请号：US316823

申请日：1994-09-30

申请人： Russell D. Eslick ,  David M. Brown ,  Lily C. Pao ,  Brian L. Dipert ,  Kurt B. Robinson

发明人： Russell D. Eslick ,  David M. Brown ,  Lily C. Pao ,  Brian L. Dipert ,  Kurt B. Robinson

IPC分类号： G11C5/14 ,  G11C13/00

CPC分类号： G11C5/14

摘要： A flash memory card is described. One flash memory card has addressable circuitry for selectively causing first, second, and third flash memories to operate in an active mode concurrently.

摘要翻译： 描述闪存卡。 一个闪存卡具有可寻址电路，用于选择性地使第一，第二和第三闪存同时以活动模式操作。

公开(公告)号：US5197034A

公开(公告)日：1993-03-23

申请号：US773247

申请日：1991-10-09

申请人： Mickey Lee Fandrich ,  Virgil N. Kynett ,  Kurt B. Robinson

发明人： Mickey Lee Fandrich ,  Virgil N. Kynett ,  Kurt B. Robinson

IPC分类号： G11C16/16 ,  G11C16/30

CPC分类号： G11C16/30 ,  G11C16/16

摘要： A non-volatile memory is described. The memory includes a memory array that includes a main block and a boot block. The memory also includes a control input for receiving a control signal. The control signal can be in a first voltage state, a second voltage state, and a third voltage state. Circuitry means is coupled to receive the control signal at the control input for (1) allowing the boot block to be updated when the control signal is in the first state and for (2) generating a power off signal to switch the memory into a substantially powered off state when the control signal is in the third voltage state. A method of controlling a non-volatile memory is also described.

摘要翻译： 描述非易失性存储器。 存储器包括包括主块和引导块的存储器阵列。 存储器还包括用于接收控制信号的控制输入。 控制信号可以处于第一电压状态，第二电压状态和第三电压状态。 电路装置被耦合以在控制输入处接收控制信号，用于（1）当控制信号处于第一状态时允许引导块被更新，并且（2）产生电源关闭信号以将存储器切换到基本上 当控制信号处于第三电压状态时，断电状态。 还描述了一种控制非易失性存储器的方法。

公开(公告)号：US07327370B2

公开(公告)日：2008-02-05

申请号：US11174662

申请日：2005-07-06

申请人： Brian D. Possley ,  David M. Puffer ,  Kurt B. Robinson ,  Ray Askew ,  James S. Chapple ,  Thomas E. Dever, II

发明人： Brian D. Possley ,  David M. Puffer ,  Kurt B. Robinson ,  Ray Askew ,  James S. Chapple ,  Thomas E. Dever, II

IPC分类号： G06F13/14 ,  G06F15/16

CPC分类号： G06F3/14 ,  G06T1/20 ,  G09G5/001

摘要： A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

摘要翻译： 存储器控制器集线器包括适于对数据执行图形操作的图形子系统，以及适于选择性地通过电连接器将图形子系统耦合到本地存储器并且通过电连接器将存储器控制器集线器耦合到图形控制器的接口电路。

公开(公告)号：US5544356A

公开(公告)日：1996-08-06

申请号：US400272

申请日：1995-03-03

申请人： Kurt B. Robinson ,  Dale K. Elbert ,  Markus A. Levy

发明人： Kurt B. Robinson ,  Dale K. Elbert ,  Markus A. Levy

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G11C16/02 ,  G11C16/34 ,  G06F17/30

CPC分类号： G06F3/0601 ,  G06F12/023 ,  G06F12/0246 ,  G06F12/0638 ,  G11C16/349 ,  G06F2003/0694 ,  G06F2212/7211 ,  Y10S707/99956 ,  Y10S707/99957

摘要： A non-volatile semiconductor memory that is erasable only in blocks is described. Each bit of the non-volatile semiconductor memory cannot be overwritten from a first logical state to a second logical state without a prior erasure. Each bit of the non-volatile semiconductor memory can be overwritten from a second logical state to a first logical state without a prior erasure. The non-volatile semiconductor memory comprises an active block for storing a first file, a reserve block for storing a second file, and a directory block. The second file is a copy of the first file. The copy is made during a clean-up operation prior to erasure of the active block. The directory block comprises a directory entry for identifying the first file.

摘要翻译： 描述了仅在块中可擦除的非易失性半导体存储器。 不存在先前的擦除，非易失性半导体存储器的每一位都不能被从第一逻辑状态重写到第二逻辑状态。 可以将非易失性半导体存储器的每一位从第二逻辑状态重写到第一逻辑状态，而无需先前擦除。 非易失性半导体存储器包括用于存储第一文件的活动块，用于存储第二文件的预留块和目录块。 第二个文件是第一个文件的副本。 在擦除活动块之前，在清理操作期间进行复印。 目录块包括用于识别第一文件的目录条目。

公开(公告)号：US5388248A

公开(公告)日：1995-02-07

申请号：US198789

申请日：1994-02-16

申请人： Kurt B. Robinson ,  Russell D. Eslick ,  Markus A. Levy ,  David M. Brown ,  Lily C. Pao ,  Brian L. Dipert

发明人： Kurt B. Robinson ,  Russell D. Eslick ,  Markus A. Levy ,  David M. Brown ,  Lily C. Pao ,  Brian L. Dipert

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06K19/07 ,  G11C5/00 ,  G11C16/02 ,  G11C16/10 ,  G11C17/00 ,  G06F13/00 ,  G06K19/067 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/102

摘要： A flash memory card is described which has a plurality of flash memories, each having a ready/busy output for indicating whether its respective one of the plurality of flash memories is busy or ready. A register circuit is provided for storing a plurality of mask data. A mode circuit is provided for choosing one of a first mode and a second mode, wherein a first mode signal is produced if the first mode is chosen and a second mode signal is produced if the second mode is chosen. A logic circuit is provided for performing logical operations with respect to the ready/busy output for each of the plurality of flash memories and the mask data in accordance with whether the first mode signal or the second mode signal is produced. If the first mode is chosen, the logic circuit produces a ready signal output for the flash memory card only if the ready/busy output of all the plurality of flash memories is ready. If the second mode is chosen, the logic circuit produces a ready signal output for the flash memory card each time any flash memory goes from being busy to being ready.

摘要翻译： 描述了一种闪存卡，其具有多个闪速存储器，每个闪速存储器具有用于指示其相应的一个闪存是忙还是准备好的就绪/忙输出。 提供了一种用于存储多个掩模数据的寄存器电路。 提供了用于选择第一模式和第二模式之一的模式电路，其中如果选择了第一模式，则产生第一模式信号，并且如果选择了第二模式，则产生第二模式信号。 提供逻辑电路，用于根据是否产生第一模式信号或第二模式信号，针对多个闪速存储器中的每一个和掩模数据执行关于就绪/忙输出的逻辑运算。 如果选择第一模式，则只有当所有多个闪存的就绪/忙输出准备就绪时，逻辑电路才会为闪存卡产生就绪信号输出。 如果选择第二模式，则每当闪存从忙到准备状态时，逻辑电路就为闪存卡产生就绪信号输出。