公开(公告)号：US08463223B2

公开(公告)日：2013-06-11

申请号：US13524909

申请日：2012-06-15

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/00

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收信道选择信号的输入端，其中微控制器提供时钟控制信号以响应于信道选择输入来动态地控制时钟信号的频率，以减少由时钟信号产生的次谐波的干扰 模拟接收机。

公开(公告)号：US20110151819A1

公开(公告)日：2011-06-23

申请号：US12641623

申请日：2009-12-18

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/10

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器和时钟合成器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端，用于提供中频输出信号的信号输出端和用于提供时钟控制信号的控制输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 数字处理器响应于信道选择输入动态地控制时钟信号的频率，以减少由数字处理器在模拟接收机上产生的次谐波的干扰。

公开(公告)号：US20130244601A1

公开(公告)日：2013-09-19

申请号：US13888745

申请日：2013-05-07

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H03J3/02

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字信号处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收频道选择信号的输入，其中微控制器提供时钟控制信号，以响应于信道选择输入动态地控制时钟信号的频率，以将子谐波放置在所选择的可容许频率 渠道。

公开(公告)号：US20120250809A1

公开(公告)日：2012-10-04

申请号：US13524909

申请日：2012-06-15

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B15/00 ,  H04L27/00

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收信道选择信号的输入端，其中微控制器提供时钟控制信号以响应于信道选择输入来动态地控制时钟信号的频率，以减少由时钟信号产生的次谐波的干扰 模拟接收机。

公开(公告)号：US08224279B2

公开(公告)日：2012-07-17

申请号：US12641623

申请日：2009-12-18

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/10

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器和时钟合成器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端，用于提供中频输出信号的信号输出端和用于提供时钟控制信号的控制输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 数字处理器响应于信道选择输入动态地控制时钟信号的频率，以减少由数字处理器在模拟接收机上产生的次谐波的干扰。

公开(公告)号：US20050058189A1

公开(公告)日：2005-03-17

申请号：US10663628

申请日：2003-09-16

申请人： Philip Yip ,  Paul Brown ,  Brian Mirkin

发明人： Philip Yip ,  Paul Brown ,  Brian Mirkin

IPC分类号： H04B1/38 ,  H04L25/03

CPC分类号： H04L25/03133 ,  H04L2025/0377

摘要： A method for training a receiving modem is disclosed. The receiving modem can be trained by a sending modem via a four-segment training procedure. During segment 1 training, the sending modem waits for silence on a transmission line between the sending modem and the receiving modem for 48 symbol intervals. Then, the sending modem performs segment 2 training by sending alternating AB symbols to the receiving modem for 64 symbol intervals. During segment 3 training, the sending modem sends CD symbols to the receiving modem for 64 symbol intervals in order to train an equalizer within the receiving modem. During segment 4 training, the sending modem continues to train the equalizer within the receiving modem by sending scrambled binary “1” symbols to the receiving modem for 48 symbol intervals. After a successful completion of the segment 4 training, the receiving modem can change to a data mode to begin detecting and receiving data from the sending modem.

摘要翻译： 公开了一种训练接收调制解调器的方法。 接收调制解调器可以由发送调制解调器通过四段训练程序进行训练。 在段1训练期间，发送调制解调器在发送调制解调器和接收调制解调器之间的传输线上等待48个符号间隔的静音。 然后，发送调制解调器通过向接收调制解调器发送交替的AB符号来执行段2训练，用于64个符号间隔。 在段3训练期间，发送调制解调器向接收调制解调器发送64个符号间隔的CD符号，以便在接收调制解调器内训练均衡器。 在段4训练期间，发送调制解调器继续通过向接收调制解调器发送加扰的二进制“1”符号用于48个符号间隔来训练接收调制解调器内的均衡器。 在成功完成第4段训练之后，接收调制解调器可以改变为数据模式，开始从发送调制解调器检测和接收数据。