公开(公告)号：US08463223B2

公开(公告)日：2013-06-11

申请号：US13524909

申请日：2012-06-15

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/00

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收信道选择信号的输入端，其中微控制器提供时钟控制信号以响应于信道选择输入来动态地控制时钟信号的频率，以减少由时钟信号产生的次谐波的干扰 模拟接收机。

公开(公告)号：US20110151819A1

公开(公告)日：2011-06-23

申请号：US12641623

申请日：2009-12-18

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/10

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器和时钟合成器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端，用于提供中频输出信号的信号输出端和用于提供时钟控制信号的控制输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 数字处理器响应于信道选择输入动态地控制时钟信号的频率，以减少由数字处理器在模拟接收机上产生的次谐波的干扰。

公开(公告)号：US20130244601A1

公开(公告)日：2013-09-19

申请号：US13888745

申请日：2013-05-07

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H03J3/02

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital signal processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to place a sub-harmonic at a tolerable frequency of a selected channel.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字信号处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收频道选择信号的输入，其中微控制器提供时钟控制信号，以响应于信道选择输入动态地控制时钟信号的频率，以将子谐波放置在所选择的可容许频率 渠道。

公开(公告)号：US20120250809A1

公开(公告)日：2012-10-04

申请号：US13524909

申请日：2012-06-15

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B15/00 ,  H04L27/00

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器，时钟合成器和微控制器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字信号处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端和用于提供IF输出信号的信号输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 微控制器具有用于接收信道选择信号的输入端，其中微控制器提供时钟控制信号以响应于信道选择输入来动态地控制时钟信号的频率，以减少由时钟信号产生的次谐波的干扰 模拟接收机。

公开(公告)号：US08224279B2

公开(公告)日：2012-07-17

申请号：US12641623

申请日：2009-12-18

申请人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

发明人： Terry Dickey ,  Gerald Champagne ,  Brian Mirkin

IPC分类号： H04B1/10

CPC分类号： H03J3/02 ,  H04B15/02 ,  H04B2215/064 ,  H04B2215/065

摘要： A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver.

摘要翻译： 射频（RF）接收机包括模拟接收机，数字处理器和时钟合成器。 模拟接收机具有用于接收RF输入信号的输入端和用于提供数字中频（IF）信号的输出端。 数字处理器具有用于接收数字IF信号的第一输入端，用于接收时钟信号的第二输入端，用于提供中频输出信号的信号输出端和用于提供时钟控制信号的控制输出端。 时钟合成器具有用于接收时钟控制信号的输入端和用于提供时钟信号的输出端。 数字处理器响应于信道选择输入动态地控制时钟信号的频率，以减少由数字处理器在模拟接收机上产生的次谐波的干扰。

公开(公告)号：US20070213021A1

公开(公告)日：2007-09-13

申请号：US11374533

申请日：2006-03-13

申请人： Dana Taipale ,  G. Tuttle ,  Gerald Champagne ,  Javier Elenes

发明人： Dana Taipale ,  G. Tuttle ,  Gerald Champagne ,  Javier Elenes

IPC分类号： H04B17/00

CPC分类号： H04B1/1027 ,  H04B17/336

摘要： A frequency modulation (FM) radio receiver includes a processing unit that may generate a magnitude value corresponding to a signal strength of each of a plurality of digital samples of a received FM signal. The receiver also includes a noise estimation unit that may filter the magnitude values using a high pass filter and may generate a noise value representative of a noise portion of the received FM signal based upon the filtered magnitude values.

摘要翻译： 一种频率调制（FM）无线电接收机包括一个处理单元，该处理单元可产生对应于所接收的FM信号的多个数字样本中的每一个的信号强度的幅度值。 接收机还包括噪声估计单元，该噪声估计单元可以使用高通滤波器对幅度值进行滤波，并且可以基于滤波的幅值产生代表所接收的FM信号的噪声部分的噪声值。

公开(公告)号：US5901225A

公开(公告)日：1999-05-04

申请号：US759611

申请日：1996-12-05

申请人： Mark A. Ireton ,  Gerald Champagne ,  Corbett A. Marler

发明人： Mark A. Ireton ,  Gerald Champagne ,  Corbett A. Marler

IPC分类号： G06F9/445 ,  H04L9/00

CPC分类号： G06F9/328 ,  G06F8/66

摘要： A system and method for performing software patches for embedded system devices in which the firmware of the system is included in non-alterable storage of the device. The patch mechanism provides a means for finding firmware errors, prototyping fixes to the errors and/or prototyping new functionality of the firmware of the embedded system. The system comprises an embedded system device coupled to an external memory. The device includes a non-alterable memory, including firmware, coupled to a processor. The device further includes a relatively small amount of patch RAM within the device also coupled to the processor. The patches are loaded from the external memory into the patch RAM. The device further includes a means for determining if one or more patches are to be applied. If the device detects a patch to be applied, the system loads the patch from the external memory into the patch RAM. The device also includes a breakpoint register. When the value of the program counter of the processor equals the value in the breakpoint register, a patch insertion occurs, i.e., the processor deviates from executing firmware to executing patch instructions. Preferably, the embedded system device comprises a single integrated circuit. The processor may include a plurality of breakpoint registers. The patch may be encrypted for increased security. Multiple patches may be chained together, and run-time patch replacement is contemplated.

摘要翻译： 一种用于对嵌入式系统设备执行软件补丁的系统和方法，其中所述系统的固件被包括在所述设备的不可更改存储器中。 补丁机制提供了一种用于查找固件错误，原型修复错误和/或原型化嵌入式系统固件的新功能的方法。 该系统包括耦合到外部存储器的嵌入式系统设备。 该设备包括耦合到处理器的不可更改的存储器，包括固件。 该设备还包括在设备内的相对少量的补丁RAM，其也耦合到处理器。 补丁从外部存储器加载到补丁RAM中。 该装置还包括用于确定是否应用一个或多个补丁的装置。 如果设备检测到要应用的补丁，则系统将补丁从外部存储器加载到补丁RAM中。 该设备还包括一个断点寄存器。 当处理器的程序计数器的值等于断点寄存器中的值时，将发生补丁插入，即处理器从执行固件偏离到执行补丁指令。 优选地，嵌入式系统设备包括单个集成电路。 处理器可以包括多个断点寄存器。 可以加密补丁以增加安全性。 可以将多个补丁链接在一起，并考虑运行时补丁更换。

公开(公告)号：US08060066B2

公开(公告)日：2011-11-15

申请号：US11850764

申请日：2007-09-06

申请人： Christopher Gregg ,  Gerald Champagne

发明人： Christopher Gregg ,  Gerald Champagne

IPC分类号： H04M3/42 ,  H04L29/08 ,  H04H20/71

CPC分类号： H04H20/34 ,  H04H20/95 ,  H04H60/73 ,  H04H2201/13

摘要： A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

摘要翻译： 一种接收机，包括第一电路，其被配置为组合来自作为广播信道的一部分传输的至少两组RDS / RBDS数据的相应软判决值，以生成一组组合值，以及第二电路，其被配置为识别指示的组合值的子集 提供了来自RDS / RBDS数据的至少两组的接收值的相对恒定的子集。

公开(公告)号：US20090068964A1

公开(公告)日：2009-03-12

申请号：US11850764

申请日：2007-09-06

申请人： Christopher Gregg ,  Gerald Champagne

发明人： Christopher Gregg ,  Gerald Champagne

IPC分类号： H04B1/02

CPC分类号： H04H20/34 ,  H04H20/95 ,  H04H60/73 ,  H04H2201/13

摘要： A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

摘要翻译： 一种接收机，包括第一电路，其被配置为组合来自作为广播信道的一部分传输的至少两组RDS / RBDS数据的相应软判决值，以生成一组组合值，以及第二电路，其被配置为识别指示的组合值的子集 提供了来自RDS / RBDS数据的至少两组的接收值的相对恒定的子集。

公开(公告)号：US20110158298A1

公开(公告)日：2011-06-30

申请号：US12649911

申请日：2009-12-30

申请人： Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes ,  Gerald Champagne ,  Michael Robert May

发明人： Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes ,  Gerald Champagne ,  Michael Robert May

IPC分类号： H04B1/38 ,  H04L27/00

CPC分类号： H04B1/38

摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.

摘要翻译： 调谐器电路包括数字信号处理器，用于产生与射频信号相关的数字数据流，以及耦合到数字信号处理器的收发器电路，并且可配置为产生具有起始部分和多个通道的芯片间通信帧。 多个信道包括携带数字数据流的一部分的第一数据信道和用于携带控制数据的控制信道。 收发器电路可配置为通过芯片间通信链路将片间通信帧发送到附加的调谐器电路。