公开(公告)号：US20050270065A1

公开(公告)日：2005-12-08

申请号：US10859211

申请日：2004-06-03

申请人： Dipankar Bhattacharya ,  Brijendra Dobriyal ,  Bernard Morris

发明人： Dipankar Bhattacharya ,  Brijendra Dobriyal ,  Bernard Morris

IPC分类号： H03K3/00 ,  H03K17/0412 ,  H03K17/06 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018585 ,  H03K17/04123 ,  H03K17/063 ,  H03K19/018521

摘要： A buffer design for an integrated circuit that not only recognizes, but improves upon the skew problem as described above that is particularly problematic in cases where the output buffer supply voltage is particularly close or the same as the voltage of the signals coming from the core of an IC. Translator-up circuits associated with output buffers are implemented in parallel with respective selective bypass circuits, allowing the translator-up circuit to be inserted into or removed from a signal path based on the voltage level of a signal received from the inner core and the voltage level required by the output buffer. When the voltage level of the “higher” voltage side is equal to the “lower” voltage signal level, the translator-up circuits are bypassed through selection by a selective bypass circuit. Thus, a selective bypass circuit is implemented together with a translator-up circuit to eliminate large signal skew, and to generally speed up circuit performance.

摘要翻译： 一种用于集成电路的缓冲器设计，其不仅识别但改进了如上所述的偏斜问题，在输出缓冲器电源电压特别接近或相同于来自芯的信号的电压的情况下，这是特别有问题的 一个IC 与输出缓冲器相关联的转换电路与相应的选择旁路电路并行实现，允许转换器升高电路基于从内核接收的信号的电压电平和电压插入或从信号路径中去除 输出缓冲区所需的电平。 当“较高”电压侧的电压电平等于“较低”电压信号电平时，通过选择旁路电路的选择旁路转换器电路。 因此，选择性旁路电路与转换器升压电路一起实现，以消除大的信号偏移，并且通常加速电路性能。