公开(公告)号：US08399958B2

公开(公告)日：2013-03-19

申请号：US12829741

申请日：2010-07-02

申请人： Byoung Hwa You

发明人： Byoung Hwa You

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse part for a semiconductor device includes an insulation layer configured to cover a conductive pattern over a substrate, a dual fuse configured to include a first pattern and a second pattern that are positioned on the same line over the insulation layer and spaced apart from each other by a certain distance, a protective layer configured to cover the dual fuse and include a first fuse box and a second fuse box that partially expose the first pattern and the second pattern, respectively, and a plurality of plugs configured to penetrate the insulation layer and electrically connect the first and second patterns to the conductive pattern. Herein, the plugs are positioned beneath the first and second fuse boxes.

摘要翻译： 用于半导体器件的熔丝部分包括被配置为覆盖衬底上的导电图案的绝缘层，双熔丝，其被配置为包括第一图案和第二图案，所述第一图案和第二图案位于绝缘层上并与每个 另一个距离保护层，被配置为覆盖双重保险丝的保护层，并且包括分别部分地暴露第一图案和第二图案的第一保险丝盒和第二保险丝盒，以及被配置为穿透绝缘层的多个插头 并将第一和第二图案电连接到导电图案。 这里，插头位于第一和第二保险丝盒的下方。

公开(公告)号：US20100055865A1

公开(公告)日：2010-03-04

申请号：US12344165

申请日：2008-12-24

申请人： Byoung-Hwa YOU ,  Seok-Young YOON

发明人： Byoung-Hwa YOU ,  Seok-Young YOON

IPC分类号： H01L21/76

CPC分类号： H01L21/3083 ,  H01L21/76224

摘要： A method of fabricating a semiconductor device includes forming a hardmask pattern over a substrate, forming a line type first photoresist pattern over the hardmask pattern, etching the hardmask pattern using the first photoresist pattern, removing the first photoresist pattern, forming a line type second photoresist pattern that cross the first photoresist pattern over the hardmask pattern, etching the hardmask pattern using the second photoresist pattern as an etch barrier, removing the second photoresist pattern, forming a trench by etching the substrate using the etched hardmask pattern as an etch barrier, and forming a device isolation region by filling the trench with an insulation layer.

摘要翻译： 制造半导体器件的方法包括在衬底上形成硬掩模图案，在硬掩模图案上形成线型第一光致抗蚀剂图案，使用第一光致抗蚀剂图案蚀刻硬掩模图案，去除第一光致抗蚀剂图案，形成线型第二光致抗蚀剂 使用第二光致抗蚀剂图案作为蚀刻阻挡层蚀刻硬掩模图案，去除第二光致抗蚀剂图案，通过使用蚀刻的硬掩模图案作为蚀刻阻挡层蚀刻衬底来形成沟槽，以及 通过用绝缘层填充沟槽来形成器件隔离区域。

公开(公告)号：US20120146183A1

公开(公告)日：2012-06-14

申请号：US13326244

申请日：2011-12-14

申请人： Seung Jin LEE ,  Byoung Hwa YOU

发明人： Seung Jin LEE ,  Byoung Hwa YOU

IPC分类号： H01L29/92

CPC分类号： H01L27/105 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/90

摘要： A technology is a semiconductor device and a method of manufacturing the same, capable of preventing characteristics of a storage node from degrading to improve operation characteristics of a device, by connecting an upper electrode of a peripheral circuit area to an active region of the peripheral circuit area and thus making charges generated in a plasma environment to be transferred to the active regions of the peripheral circuit area. The method includes forming a landing contact plug on a semiconductor substrate in a cell area, forming a storage node contact plug connected to the landing contact plug and a dummy contact plug on the semiconductor substrate in a peripheral circuit area, forming a lower electrode connected to the storage node contact plug, and forming an upper electrode on the lower electrode and the dummy contact plug.

摘要翻译： 一种技术是半导体器件及其制造方法，其能够通过将外围电路区域的上部电极连接到外围电路的有源区域来防止存储节点的特性劣化以提高器件的操作特性 从而使在等离子体环境中产生的电荷转移到外围电路区域的有源区。 该方法包括在单元区域中的半导体基板上形成着接触插塞，在外围电路区域中形成连接到着陆接触插塞的存储节点接触插塞和半导体衬底上的虚拟接触插塞，形成连接到 存储节点接触插塞，并且在下电极和虚拟接触插塞上形成上电极。

公开(公告)号：US20110001213A1

公开(公告)日：2011-01-06

申请号：US12829741

申请日：2010-07-02

申请人： Byoung-Hwa You

发明人： Byoung-Hwa You

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse part for a semiconductor device includes an insulation layer configured to cover a conductive pattern over a substrate, a dual fuse configured to include a first pattern and a second pattern that are positioned on the same line over the insulation layer and spaced apart from each other by a certain distance, a protective layer configured to cover the dual fuse and include a first fuse box and a second fuse box that partially expose the first pattern and the second pattern, respectively, and a plurality of plugs configured to penetrate the insulation layer and electrically connect the first and second patterns to the conductive pattern. Herein, the plugs are positioned beneath the first and second fuse boxes.

摘要翻译： 用于半导体器件的熔丝部分包括被配置为覆盖衬底上的导电图案的绝缘层，双熔丝，其被配置为包括第一图案和第二图案，所述第一图案和第二图案位于绝缘层上并与每个 另一个距离保护层，被配置为覆盖双重保险丝的保护层，并且包括分别部分地暴露第一图案和第二图案的第一保险丝盒和第二保险丝盒，以及被配置为穿透绝缘层的多个插头 并将第一和第二图案电连接到导电图案。 这里，插头位于第一和第二保险丝盒的下方。